Chia-Lin Yang

2008
39	EE	Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang: A progressive-ILP based routing algorithm for cross-referencing biochips. DAC 2008: 284-289
38	EE	Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng: Energy-Aware Flash Memory Management in Virtual Memory System. IEEE Trans. VLSI Syst. 16(8): 952-964 (2008)
37	EE	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 1928-1941 (2008)
36	EE	Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang: Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 643-653 (2008)
2007
35	EE	Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen: Cache leakage control mechanism for hard real-time systems. CASES 2007: 248-256
34	EE	Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang, Ku-Jei King: Energy-efficient real-time task scheduling with task rejection. DATE 2007: 1629-1634
33	EE	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. ICCAD 2007: 752-757
32	EE	Shao-Yi Chien, Chi-Sheng Shih, Mong-Kai Ku, Chia-Lin Yang, Yao-Wen Chang, Tei-Wei Kuo, Liang-Gee Chen: 3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. ICME 2007: 9
31	EE	Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. ISLPED 2007: 92-97
30	EE	Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang: Efficient obstacle-avoiding rectilinear steiner tree construction. ISPD 2007: 127-134
29	EE	Wei-Hsuan Hung, Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang, Alan P. Su: An architectural co-synthesis algorithm for energy-aware network-on-chip design. SAC 2007: 680-684
28	EE	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Temporal floorplanning using the three-dimensional transitive closure subGraph. ACM Trans. Design Autom. Electr. Syst. 12(4): (2007)
27	EE	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation. JETC 3(3): (2007)
2006
26	EE	Chia-Lin Yang, Shun-Ying Wang, Yi-Jung Chen: Branch Behavior Characterization for Multimedia Applications. Asia-Pacific Computer Systems Architecture Conference 2006: 523-530
25	EE	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Placement of digital microfluidic biochips using the t-tree formulation. DAC 2006: 931-934
24	EE	Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King: Hierarchical value cache encoding for off-chip data bus. ISLPED 2006: 143-146
23	EE	Hung-Wei Tseng, Han-Lin Li, Chia-Lin Yang: An energy-efficient virtual memory system with flash memory as the secondary storage. ISLPED 2006: 418-423
22	EE	Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang: A Space-Efficient Caching Mechanism for Flash-Memory Address Translation. ISORC 2006: 64-71
2005
21	EE	Chun-Yang Chen, Chia-Lin Yang, Shih-Hao Hung: Cache Leakage Management for Multi-programming Workloads. Asia-Pacific Computer Systems Architecture Conference 2005: 736-749
20	EE	Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang: Joint exploration of architectural and physical design spaces with thermal consideration. ISLPED 2005: 123-126
19	EE	Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen: Reconfigurable Platform for Content Science Research. RTCSA 2005: 481-486
18	EE	Chia-Lin Yang, Hong-Wei Tseng, Chia-Chiang Ho, Ja-Ling Wu: Software-Controlled Cache Architecture for Energy Efficiency. IEEE Trans. Circuits Syst. Video Techn. 15(5): 634-644 (2005)
2004
17	EE	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen: Temporal floorplanning using 3D-subTCG. ASP-DAC 2004: 725-730
16	EE	Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang: Energy-efficient flash-memory storage systems with an interrupt-emulation mechanism. CODES+ISSS 2004: 134-139
15	EE	Yen-Jen Chang, Chia-Lin Yang, Feipei Lai: Value-Conscious Cache: Simple Technique for Reducing Cache Access Power. DATE 2004: 16-21
14	EE	Jian-Jia Chen, Heng-Ruey Hsu, Kai-Hsiang Chuang, Chia-Lin Yang, Ai-Chun Pang, Tei-Wei Kuo: Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations. ECRTS 2004: 101-108
13	EE	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Temporal floorplanning using the T-tree formulation. ICCAD 2004: 300-305
12	EE	Chia-Lin Yang, Chien-Hao Lee: HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction. ISLPED 2004: 114-119
11	EE	Tse-Tsung Shih, Chia-Lin Yang, Yi-Shin Tung: Workload Characterization of the H.264/AVC Decoder. PCM (2) 2004: 957-966
10	EE	Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang: Profit-driven uniprocessor scheduling with energy and timing constraints. SAC 2004: 834-840
9	EE	Yen-Jen Chang, Feipei Lai, Chia-Lin Yang: Zero-aware asymmetric SRAM cell for reducing cache power in writing zero. IEEE Trans. VLSI Syst. 12(8): 827-836 (2004)
8	EE	Chia-Lin Yang, Alvin R. Lebeck, Hung-Wei Tseng, Chien-Hao Lee: Tolerating memory latency through push prefetching for pointer-intensive applications. TACO 1(4): 445-475 (2004)
2003
7	EE	Yen-Jen Chang, Chia-Lin Yang, Feipei Lai: A power-aware SWDR cell for reducing cache write power. ISLPED 2003: 14-17
2002
6	EE	Wan-Chun Ma, Chia-Lin Yang: Using Intel Streaming SIMD Extensions for 3D Geometry Processing. IEEE Pacific Rim Conference on Multimedia 2002: 1080-1087
5	EE	Chia-Lin Yang, Alvin R. Lebeck: A Programmable Memory Hierarchy for Prefetching Linked Data Structures. ISHPC 2002: 160-174
2000
4	EE	Chia-Lin Yang, Alvin R. Lebeck: Push vs. pull: data movement for linked data structures. ICS 2000: 176-186
3	EE	Chia-Lin Yang, Barton Sano, Alvin R. Lebeck: Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions. IEEE Trans. Computers 49(9): 934-946 (2000)
1999
2	EE	Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, Mithuna Thottethodi: Annotated Memory References: A Mechanism for Informed Cache Management. Euro-Par 1999: 1251-1254
1998
1	EE	Chia-Lin Yang, Barton Sano, Alvin R. Lebeck: Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications. MICRO 1998: 14-24

Coauthor Index

1	Yao-Wen Chang	[13] [17] [19] [20] [25] [27] [28] [30] [31] [32] [33] [36] [37] [39]
2	Yen-Jen Chang	[7] [9] [15]
3	Yen-Sheng Chang	[29]
4	Chun-Yang Chen	[21]
5	Hsin-Lung Chen	[17]
6	Jian-Jia Chen	[10] [14] [34] [35]
7	Liang-Gee Chen	[19] [32]
8	Szu-Yu Chen	[30] [36]
9	Yi-Jung Chen	[26] [29] [35]
10	Jaw-Wei Chi	[35]
11	Shao-Yi Chien	[19] [32]
12	Kai-Hsiang Chuang	[14]
13	Chia-Chiang Ho	[18]
14	Heng-Ruey Hsu	[14]
15	Shih-Hao Hung	[21]
16	Wei-Hsuan Hung	[29]
17	Ku-Jei King	[24] [34]
18	Mong-Kai Ku	[19] [32]
19	Tei-Wei Kuo	[10] [14] [16] [19] [22] [32] [34]
20	Feipei Lai	[7] [9] [15]
21	Alvin R. Lebeck	[1] [2] [3] [4] [5] [8]
22	Chien-Hao Lee	[8] [12]
23	Chi-Feng Li	[30] [31] [36]
24	Han-Lin Li	[23] [38]
25	Chung-Hsiang Lin	[24]
26	Chung-Wei Lin	[30] [36]
27	Wan-Chun Ma	[6]
28	Ai-Chun Pang	[14]
29	David R. Raymond	[2]
30	Barton Sano	[1] [3]
31	Sachin S. Sapatnekar	[39]
32	Chi-Sheng Shih	[19] [32]
33	Tse-Tsung Shih	[11]
34	Alan P. Su	[29]
35	Mithuna Thottethodi	[2]
36	Hong-Wei Tseng	[18]
37	Hung-Wei Tseng	[8] [23] [38]
38	Yi-Shin Tung	[11]
39	Shun-Ying Wang	[26]
40	Chin-Hsien Wu	[16] [22]
41	Ja-Ling Wu	[18]
42	Yen-Wei Wu	[20]
43	Ping-Hung Yuh	[13] [17] [20] [25] [27] [28] [31] [33] [37] [39]

Colors in the list of coauthors