| 2008 |
|---|
| 13 | EE | Ping-Hung Yuh,
Sachin S. Sapatnekar,
Chia-Lin Yang,
Yao-Wen Chang:
A progressive-ILP based routing algorithm for cross-referencing biochips.
DAC 2008: 284-289 |
| 12 | EE | Ping-Hung Yuh,
Chia-Lin Yang,
Yao-Wen Chang:
BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 1928-1941 (2008) |
| 11 | EE | Tung-Chieh Chen,
Ping-Hung Yuh,
Yao-Wen Chang,
Few-Juh Huang,
T.-Y. Liu:
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1621-1634 (2008) |
| 2007 |
|---|
| 10 | EE | Tung-Chieh Chen,
Ping-Hung Yuh,
Yao-Wen Chang,
Fwu-Juh Huang,
Denny Liu:
MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs.
DAC 2007: 447-452 |
| 9 | EE | Ping-Hung Yuh,
Chia-Lin Yang,
Yao-Wen Chang:
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips.
ICCAD 2007: 752-757 |
| 8 | EE | Chi-Feng Li,
Ping-Hung Yuh,
Chia-Lin Yang,
Yao-Wen Chang:
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs.
ISLPED 2007: 92-97 |
| 7 | EE | Ping-Hung Yuh,
Chia-Lin Yang,
Yao-Wen Chang:
Temporal floorplanning using the three-dimensional transitive closure subGraph.
ACM Trans. Design Autom. Electr. Syst. 12(4): (2007) |
| 6 | EE | Ping-Hung Yuh,
Chia-Lin Yang,
Yao-Wen Chang:
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation.
JETC 3(3): (2007) |
| 2006 |
|---|
| 5 | EE | Ping-Hung Yuh,
Chia-Lin Yang,
Yao-Wen Chang:
Placement of digital microfluidic biochips using the t-tree formulation.
DAC 2006: 931-934 |
| 2005 |
|---|
| 4 | | Jia-Wei Fang,
I-Jye Lin,
Ping-Hung Yuh,
Yao-Wen Chang,
Jyh-Herng Wang:
A routing algorithm for flip-chip design.
ICCAD 2005: 753-758 |
| 3 | EE | Yen-Wei Wu,
Chia-Lin Yang,
Ping-Hung Yuh,
Yao-Wen Chang:
Joint exploration of architectural and physical design spaces with thermal consideration.
ISLPED 2005: 123-126 |
| 2004 |
|---|
| 2 | EE | Ping-Hung Yuh,
Chia-Lin Yang,
Yao-Wen Chang,
Hsin-Lung Chen:
Temporal floorplanning using 3D-subTCG.
ASP-DAC 2004: 725-730 |
| 1 | EE | Ping-Hung Yuh,
Chia-Lin Yang,
Yao-Wen Chang:
Temporal floorplanning using the T-tree formulation.
ICCAD 2004: 300-305 |
