| |
| 2008 | ||
|---|---|---|
| 4 | EE | Uday Padmanabhan, Janet Meiling Wang, Jiang Hu: Robust Clock Tree Routing in the Presence of Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1385-1397 (2008) |
| 2007 | ||
| 3 | EE | Bharat Sukhwani, Uday Padmanabhan, Janet Meiling Wang: Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design CoRR abs/0710.4633: (2007) |
| 2006 | ||
| 2 | EE | Uday Padmanabhan, Janet Meiling Wang, Jiang Hu: Statistical clock tree routing for robustness to process variations. ISPD 2006: 149-156 |
| 2005 | ||
| 1 | EE | Bharat B. Sukhwani, Uday Padmanabhan, Janet Meiling Wang: Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design. DATE 2005: 758-763 |
| 1 | Jiang Hu | [2] [4] |
| 2 | Bharat Sukhwani | [3] |
| 3 | Bharat B. Sukhwani | [1] |
| 4 | Janet Meiling Wang (Janet Meiling Wang Roveda) | [1] [2] [3] [4] |