2009 |
29 | EE | Deming Chen,
Russell Tessier,
Mojy C. Chian,
Steve Trimberger,
Shinobu Fujita,
André DeHon,
Deming Chen:
CMOS vs Nano: comrades or rivals?
FPGA 2009: 121-122 |
28 | EE | Deming Chen,
Russell Tessier,
Mojy C. Chian,
Steve Trimberger,
Shinobu Fujita,
André DeHon,
Deming Chen:
CMOS vs Nano: comrades or rivals?
FPGA 2009: 121-122 |
27 | EE | Chen Dong,
Scott Chilstedt,
Deming Chen:
FPCNA: a field programmable carbon nanotube array.
FPGA 2009: 161-170 |
26 | EE | Brian Greskamp,
Lu Wan,
Ulya R. Karpuzcu,
Jeffrey J. Cook,
Josep Torrellas,
Deming Chen,
Craig B. Zilles:
Blueshift: Designing processors for timing speculation from the ground up.
HPCA 2009: 213-224 |
2008 |
25 | EE | Shoaib Akram,
Scott Cromar,
Gregory Lucas,
Alexandros Papakonstantinou,
Deming Chen:
VEBoC: Variation and error-aware design for billions of devices on a chip.
ASP-DAC 2008: 803-808 |
24 | EE | Quang Dinh,
Deming Chen,
Martin D. F. Wong:
Efficient ASIP design for configurable processors with fine-grained resource sharing.
FPGA 2008: 99-106 |
23 | EE | Alexandros Papakonstantinou,
Deming Chen,
Wen-mei W. Hwu:
Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor.
SASP 2008: 20-25 |
22 | EE | Lei Cheng,
Deming Chen,
Martin D. F. Wong:
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction.
ACM Trans. Design Autom. Electr. Syst. 13(2): (2008) |
21 | EE | Lei Cheng,
Deming Chen,
Martin D. F. Wong:
DDBDD: Delay-Driven BDD Synthesis for FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1203-1213 (2008) |
2007 |
20 | EE | Deming Chen,
Jason Cong,
Yiping Fan,
Zhiru Zhang:
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs.
ASP-DAC 2007: 529-534 |
19 | EE | Lei Cheng,
Deming Chen,
Martin D. F. Wong:
GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches.
DAC 2007: 318-323 |
18 | EE | Lei Cheng,
Deming Chen,
Martin D. F. Wong:
DDBDD: Delay-Driven BDD Synthesis for FPGAs.
DAC 2007: 910-915 |
17 | EE | Lei Cheng,
Deming Chen,
Martin D. F. Wong,
Mike Hutton,
Jason Govig:
Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains.
ICCAD 2007: 370-375 |
16 | EE | Chen Dong,
Deming Chen,
Sansiri Tanachutiwat,
Wei Wang:
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture.
ICCAD 2007: 758-764 |
2006 |
15 | EE | Lei Cheng,
Liang Deng,
Deming Chen,
Martin D. F. Wong:
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction.
DAC 2006: 117-120 |
14 | EE | Joey Y. Lin,
Deming Chen,
Jason Cong:
Optimal simultaneous mapping and clustering for FPGA delay optimization.
DAC 2006: 472-477 |
13 | EE | Deming Chen,
Jason Cong,
Yiping Fan,
Junjuan Xu:
Optimality study of resource binding with multi-Vdds.
DAC 2006: 580-585 |
12 | EE | Deming Chen,
Jason Cong,
Junjuan Xu:
Optimal simultaneous module and multivoltage assignment for low power.
ACM Trans. Design Autom. Electr. Syst. 11(2): 362-386 (2006) |
11 | EE | Deming Chen,
Jason Cong,
Peichen Pan:
FPGA Design Automation: A Survey.
Foundations and Trends in Electronic Design Automation 1(3): (2006) |
2005 |
10 | EE | Deming Chen,
Jason Cong,
Junjuan Xu:
Optimal module and voltage assignment for low-power.
ASP-DAC 2005: 850-855 |
9 | EE | Fei Li,
Yizhou Lin,
Lei He,
Deming Chen,
Jason Cong:
Power modeling and characteristics of field programmable gate arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1712-1724 (2005) |
2004 |
8 | EE | Deming Chen,
Jason Cong:
Register binding and port assignment for multiplexer optimization.
ASP-DAC 2004: 68-73 |
7 | EE | Deming Chen,
Jason Cong,
Fei Li,
Lei He:
Low-power technology mapping for FPGA architectures with dual supply voltages.
FPGA 2004: 109-117 |
6 | EE | Deming Chen,
Jason Cong:
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs.
ICCAD 2004: 752-759 |
5 | EE | Deming Chen,
Jason Cong:
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages.
ISLPED 2004: 70-73 |
2003 |
4 | EE | Fei Li,
Deming Chen,
Lei He,
Jason Cong:
Architecture evaluation for power-efficient FPGAs.
FPGA 2003: 175-184 |
3 | EE | Deming Chen,
Jason Cong,
Yiping Fan:
Low-power high-level synthesis for FPGA architectures.
ISLPED 2003: 134-139 |
2 | EE | Deming Chen,
Jason Cong,
Milos D. Ercegovac,
Zhijun Huang:
Performance-driven mapping for CPLD architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1424-1431 (2003) |
2001 |
1 | EE | Deming Chen,
Jason Cong,
Milos D. Ercegovac,
Zhijun Huang:
Performance-driven mapping for CPLD architectures.
FPGA 2001: 39-47 |