dblp.uni-trier.dewww.uni-trier.de

Deming Chen

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2009
29EEDeming Chen, Russell Tessier, Mojy C. Chian, Steve Trimberger, Shinobu Fujita, André DeHon, Deming Chen: CMOS vs Nano: comrades or rivals? FPGA 2009: 121-122
28EEDeming Chen, Russell Tessier, Mojy C. Chian, Steve Trimberger, Shinobu Fujita, André DeHon, Deming Chen: CMOS vs Nano: comrades or rivals? FPGA 2009: 121-122
27EEChen Dong, Scott Chilstedt, Deming Chen: FPCNA: a field programmable carbon nanotube array. FPGA 2009: 161-170
26EEBrian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles: Blueshift: Designing processors for timing speculation from the ground up. HPCA 2009: 213-224
2008
25EEShoaib Akram, Scott Cromar, Gregory Lucas, Alexandros Papakonstantinou, Deming Chen: VEBoC: Variation and error-aware design for billions of devices on a chip. ASP-DAC 2008: 803-808
24EEQuang Dinh, Deming Chen, Martin D. F. Wong: Efficient ASIP design for configurable processors with fine-grained resource sharing. FPGA 2008: 99-106
23EEAlexandros Papakonstantinou, Deming Chen, Wen-mei W. Hwu: Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor. SASP 2008: 20-25
22EELei Cheng, Deming Chen, Martin D. F. Wong: A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. ACM Trans. Design Autom. Electr. Syst. 13(2): (2008)
21EELei Cheng, Deming Chen, Martin D. F. Wong: DDBDD: Delay-Driven BDD Synthesis for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1203-1213 (2008)
2007
20EEDeming Chen, Jason Cong, Yiping Fan, Zhiru Zhang: High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. ASP-DAC 2007: 529-534
19EELei Cheng, Deming Chen, Martin D. F. Wong: GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches. DAC 2007: 318-323
18EELei Cheng, Deming Chen, Martin D. F. Wong: DDBDD: Delay-Driven BDD Synthesis for FPGAs. DAC 2007: 910-915
17EELei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig: Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. ICCAD 2007: 370-375
16EEChen Dong, Deming Chen, Sansiri Tanachutiwat, Wei Wang: Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture. ICCAD 2007: 758-764
2006
15EELei Cheng, Liang Deng, Deming Chen, Martin D. F. Wong: A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. DAC 2006: 117-120
14EEJoey Y. Lin, Deming Chen, Jason Cong: Optimal simultaneous mapping and clustering for FPGA delay optimization. DAC 2006: 472-477
13EEDeming Chen, Jason Cong, Yiping Fan, Junjuan Xu: Optimality study of resource binding with multi-Vdds. DAC 2006: 580-585
12EEDeming Chen, Jason Cong, Junjuan Xu: Optimal simultaneous module and multivoltage assignment for low power. ACM Trans. Design Autom. Electr. Syst. 11(2): 362-386 (2006)
11EEDeming Chen, Jason Cong, Peichen Pan: FPGA Design Automation: A Survey. Foundations and Trends in Electronic Design Automation 1(3): (2006)
2005
10EEDeming Chen, Jason Cong, Junjuan Xu: Optimal module and voltage assignment for low-power. ASP-DAC 2005: 850-855
9EEFei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong: Power modeling and characteristics of field programmable gate arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1712-1724 (2005)
2004
8EEDeming Chen, Jason Cong: Register binding and port assignment for multiplexer optimization. ASP-DAC 2004: 68-73
7EEDeming Chen, Jason Cong, Fei Li, Lei He: Low-power technology mapping for FPGA architectures with dual supply voltages. FPGA 2004: 109-117
6EEDeming Chen, Jason Cong: DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs. ICCAD 2004: 752-759
5EEDeming Chen, Jason Cong: Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. ISLPED 2004: 70-73
2003
4EEFei Li, Deming Chen, Lei He, Jason Cong: Architecture evaluation for power-efficient FPGAs. FPGA 2003: 175-184
3EEDeming Chen, Jason Cong, Yiping Fan: Low-power high-level synthesis for FPGA architectures. ISLPED 2003: 134-139
2EEDeming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang: Performance-driven mapping for CPLD architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1424-1431 (2003)
2001
1EEDeming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang: Performance-driven mapping for CPLD architectures. FPGA 2001: 39-47

Coauthor Index

1Shoaib Akram [25]
2Lei Cheng [15] [17] [18] [19] [21] [22]
3Mojy C. Chian [29]
4Scott Chilstedt [27]
5Jason Cong [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [20]
6Jeffrey J. Cook [26]
7Scott Cromar [25]
8André DeHon [29]
9Liang Deng [15]
10Quang Dinh [24]
11Chen Dong [16] [27]
12Milos D. Ercegovac [1] [2]
13Yiping Fan [3] [13] [20]
14Shinobu Fujita [29]
15Jason Govig [17]
16Brian Greskamp [26]
17Lei He [4] [7] [9]
18Zhijun Huang [1] [2]
19Michael Hutton (Michael D. Hutton, Mike Hutton) [17]
20Wen-mei W. Hwu [23]
21Ulya R. Karpuzcu [26]
22Fei Li [4] [7] [9]
23Joey Y. Lin [14]
24Yizhou Lin [9]
25Gregory Lucas [25]
26Peichen Pan [11]
27Alexandros Papakonstantinou [23] [25]
28Sansiri Tanachutiwat [16]
29Russell Tessier [29]
30Josep Torrellas [26]
31Steve Trimberger [29]
32Lu Wan [26]
33Wei Wang [16]
34Martin D. F. Wong (D. F. Wong) [15] [17] [18] [19] [21] [22] [24]
35Junjuan Xu [10] [12] [13]
36Zhiru Zhang [20]
37Craig B. Zilles [26]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)