| 2008 |
|---|
| 6 | EE | Rolf Drechsler,
Stephan Eggersglüß,
Görschwin Fey,
Andreas Glowatz,
Friedrich Hapke,
Jürgen Schlöffel,
Daniel Tille:
On Acceleration of SAT-Based ATPG for Industrial Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1329-1333 (2008) |
| 2007 |
|---|
| 5 | EE | Rene Krenz-Baath,
Andreas Glowatz,
Jürgen Schlöffel:
Computation and Application of Absolute Dominators in Industrial Designs.
European Test Symposium 2007: 137-144 |
| 4 | EE | Stephan Eggersglüß,
Daniel Tille,
Görschwin Fey,
Rolf Drechsler,
Andreas Glowatz,
Friedrich Hapke,
Jürgen Schlöffel:
Experimental Studies on SAT-Based ATPG for Gate Delay Faults.
ISMVL 2007: 6 |
| 3 | EE | Stephan Eggersglüß,
Görschwin Fey,
Rolf Drechsler,
Andreas Glowatz,
Friedrich Hapke,
Jürgen Schlöffel:
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults.
MEMOCODE 2007: 181-187 |
| 2006 |
|---|
| 2 | EE | Harald P. E. Vranken,
Sandeep Kumar Goel,
Andreas Glowatz,
Jürgen Schlöffel,
Friedrich Hapke:
Fault detection and diagnosis with parity trees for space compaction of test responses.
DAC 2006: 1095-1098 |
| 2005 |
|---|
| 1 | EE | Junhao Shi,
Görschwin Fey,
Rolf Drechsler,
Andreas Glowatz,
Friedrich Hapke,
Jürgen Schlöffel:
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits.
ISVLSI 2005: 212-217 |
