2008 |
23 | EE | Jun Zhu,
Ingo Sander,
Axel Jantsch:
Energy efficient streaming applications with guaranteed throughput on MPSoCs.
EMSOFT 2008: 119-128 |
22 | EE | Jun Zhu,
Ingo Sander,
Axel Jantsch:
Performance analysis of reconfiguration in adaptive real-time streaming applications.
ESTImedia 2008: 53-58 |
21 | EE | Ingo Sander,
Axel Jantsch:
Modelling Adaptive Systems in ForSyDe.
Electr. Notes Theor. Comput. Sci. 200(2): 39-54 (2008) |
20 | EE | Tarvo Raudvere,
Ingo Sander,
Axel Jantsch:
Application and Verification of Local Nonsemantic-Preserving Transformations in System Design.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1091-1103 (2008) |
2007 |
19 | EE | Tarvo Raudvere,
Ingo Sander,
Axel Jantsch:
A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops.
ACM Great Lakes Symposium on VLSI 2007: 353-358 |
18 | EE | Tarvo Raudvere,
Ingo Sander,
Axel Jantsch:
Synchronization after design refinements with sensitive delay elements.
CODES+ISSS 2007: 21-26 |
17 | EE | Andreas Herrholz,
Frank Oppenheimer,
Philipp A. Hartmann,
Andreas Schallenberg,
Wolfgang Nebel,
Christoph Grimm,
Markus Damm,
Jan Haase,
F. Brame,
Fernando Herrera,
Eugenio Villar,
Ingo Sander,
Axel Jantsch,
Anne-Marie Fouilliart,
M. Martinez:
The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems.
FPL 2007: 396-401 |
16 | EE | Zhonghai Lu,
Jonas Sicking,
Ingo Sander,
Axel Jantsch:
Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures.
IEEE International Workshop on Rapid System Prototyping 2007: 143-149 |
2006 |
15 | EE | Zhonghai Lu,
Ingo Sander,
Axel Jantsch:
Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication.
DSD 2006: 37-44 |
14 | EE | Rikard Thid,
Ingo Sander,
Axel Jantsch:
Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads.
DSD 2006: 681-688 |
2005 |
13 | EE | Zhonghai Lu,
Axel Jantsch,
Ingo Sander:
Feasibility analysis of messages for on-chip networks using wormhole routing.
ASP-DAC 2005: 960-964 |
12 | EE | Zhonghai Lu,
Ingo Sander,
Axel Jantsch:
Refinement of Perfectly Synchronous Communication Model.
FDL 2005: 453-465 |
11 | | Tarvo Raudvere,
Ashish Kumar Singh,
Ingo Sander,
Axel Jantsch:
System level verification of digital signal processing applications based on the polynomial abstraction technique.
ICCAD 2005: 285-290 |
2004 |
10 | EE | Tarvo Raudvere,
Ashish Kumar Singh,
Ingo Sander,
Axel Jantsch:
Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits.
DATE 2004: 690-691 |
9 | EE | Ingo Sander,
Axel Jantsch:
System modeling and transformational design refinement in ForSyDe [formal system design].
IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 17-32 (2004) |
2003 |
8 | EE | Tarvo Raudvere,
Ingo Sander,
Ashish Kumar Singh,
Axel Jantsch:
Verification of design decisions in ForSyDe.
CODES+ISSS 2003: 176-181 |
7 | EE | Ingo Sander,
Axel Jantsch,
Zhonghai Lu:
Development and Application of Design Transformations in ForSyDe.
DATE 2003: 10364-10369 |
2002 |
6 | EE | Ingo Sander,
Axel Jantsch:
Transformation based communication and clock domain refinement for system design.
DAC 2002: 281-286 |
5 | EE | Ingo Sander,
Axel Jantsch,
Zhonghai Lu:
A Case Study of Hardware and Software Synthesis in ForSyDe.
ISSS 2002: 86-91 |
2001 |
4 | EE | Axel Jantsch,
Ingo Sander,
Wenbiao Wu:
The usage of stochastic processes in embedded system specifications.
CODES 2001: 5-10 |
2000 |
3 | EE | Axel Jantsch,
Ingo Sander:
On the roles of functions and objects in system specification.
CODES 2000: 8-12 |
1999 |
2 | EE | Ingo Sander,
Axel Jantsch:
System synthesis utilizing a layered functional model.
CODES 1999: 136-140 |
1 | | Ingo Sander,
Axel Jantsch:
Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons.
VLSI Design 1999: 318-323 |