Gerhard W. Dueck

2009
28	EE	Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler: Reversible Logic Synthesis with Output Permutation. VLSI Design 2009: 189-194
2008
27	EE	Nathan O. Scott, Gerhard W. Dueck: Pairwise decomposition of toffoli gates in a quantum circuit. ACM Great Lakes Symposium on VLSI 2008: 231-236
26	EE	Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große: Quantified Synthesis of Reversible Logic. DATE 2008: 1015-1020
25	EE	Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. ISMVL 2008: 214-219
24	EE	Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler: RevLib: An Online Resource for Reversible Functions and Reversible Circuits. ISMVL 2008: 220-225
23	EE	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, C. Negrevergne: Quantum Circuit Simplification and Level Compaction. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 436-444 (2008)
2007
22	EE	Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler: Exact sat-based toffoli network synthesis. ACM Great Lakes Symposium on VLSI 2007: 96-101
21	EE	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Techniques for the synthesis of reversible Toffoli networks. ACM Trans. Design Autom. Electr. Syst. 12(4): (2007)
2005
20	EE	Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck: Quantum Circuit Simplification Using Templates. DATE 2005: 1208-1213
19	EE	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Synthesis of Fredkin-Toffoli reversible networks. IEEE Trans. VLSI Syst. 13(6): 765-769 (2005)
18	EE	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Toffoli network synthesis with templates. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 807-817 (2005)
2004
17	EE	D. Michael Miller, Gerhard W. Dueck, Dmitri Maslov: A Synthesis Method for MVL Reversible Logi. ISMVL 2004: 74-80
16	EE	Dmitri Maslov, Gerhard W. Dueck: Reversible cascades with minimal garbage. IEEE Trans. on CAD of Integrated Circuits and Systems 23(11): 1497-1509 (2004)
2003
15	EE	D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck: A transformation based algorithm for reversible logic synthesis. DAC 2003: 318-323
14	EE	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Fredkin/Toffoli Templates for Reversible Logic Synthesis. ICCAD 2003: 256-261
13	EE	D. Michael Miller, Gerhard W. Dueck: On the Size of Multiple-Valued Decision Diagrams. ISMVL 2003: 235-240
12	EE	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Simplification of Toffoli Networks via Templates. SBCCI 2003: 53-
2001
11		Jon T. Butler, Gerhard W. Dueck, Svetlana N. Yanushkevich, Vlad P. Shmerko: On the number of generators for transeunt triangles. Discrete Applied Mathematics 108(3): 309-316 (2001)
10	EE	Ping Wang, Gerhard W. Dueck, S. MacMillan: Using simulated annealing to construct extremal graphs. Discrete Mathematics 235(1-3): 125-135 (2001)
2000
9	EE	Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko: Experiments on FPRM Expressions for Partially Symmetric Logic Functions. ISMVL 2000: 141-146
8	EE	Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko, Svetlana N. Yanushkevich: Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions". IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1386-1388 (2000)
1999
7	EE	Gerhard W. Dueck, Mou Hu, Blair Fraser: A Super Switch Algebra for Quantum Device Based Systems. ISMVL 1999: 118-124
1998
6	EE	Blair Fraser, Gerhard W. Dueck: Multiple-Valued Logic Minimization using Universal Literals and Cost Tables. ISMVL 1998: 239-244
1994
5		Gerhard W. Dueck, Jon T. Butler: Multiple-Valued Logic Operations with Universal Literals. ISMVL 1994: 73-79
1992
4		Gerhard W. Dueck: Direct Cover MVL Minimization with Cost-Tables. ISMVL 1992: 58-65
3		Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler: Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. ISMVL 1992: 66-74
1991
2		Gerhard W. Dueck, G. H. John van Rees: On the Maximum Number of Implicants Needed to Cover a Multiple-Valued Logic Function Using Window Literals. ISMVL 1991: 280-286
1990
1		Gerhard W. Dueck, D. Michael Miller: RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. ISMVL 1990: 136-143

Coauthor Index

1	Jon T. Butler	[3] [5] [8] [9] [11]
2	Xiaobo Chen	[22]
3	Rolf Drechsler	[22] [24] [25] [28]
4	Robert C. Earle	[3]
5	Blair Fraser	[6] [7]
6	Daniel Große	[22] [24] [25] [26] [28]
7	Mou Hu	[7]
8	Hoang M. Le	[26]
9	S. MacMillan	[10]
10	Dmitri Maslov	[12] [14] [15] [16] [17] [18] [19] [20] [21] [23]
11	D. Michael Miller	[1] [12] [13] [14] [15] [17] [18] [19] [20] [21] [23]
12	C. Negrevergne	[23]
13	G. H. John van Rees	[2]
14	Nathan O. Scott	[27]
15	Vlad P. Shmerko	[8] [9] [11]
16	Lisa Teuber	[24]
17	Parthasarathy P. Tirumalai	[3]
18	Ping Wang	[10]
19	Robert Wille	[24] [25] [26] [28]
20	Svetlana N. Yanushkevich	[8] [9] [11]
21	Christina Young	[20]

Colors in the list of coauthors