2008 | ||
---|---|---|
58 | EE | Hiran Tennakoon, Carl Sechen: Nonconvex Gate Delay Modeling and Delay Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1583-1594 (2008) |
2007 | ||
57 | EE | Sheng Sun, Carl Sechen: Post-layout comparison of high performance 64b static adders in energy-delay space. ICCD 2007: 401-408 |
2006 | ||
56 | EE | Jinyao Zhang, Miodrag Vujkovic, David Wadkins, Carl Sechen: Post-layout energy-delay analysis of parallel multipliers. ISCAS 2006 |
2005 | ||
55 | EE | Hiran Tennakoon, Carl Sechen: Efficient and accurate gate sizing with piecewise convex delay models. DAC 2005: 807-812 |
54 | EE | Xinyu Guo, Carl Sechen: High Speed Redundant Adder and Divider in Output Prediction Logic. ISVLSI 2005: 34-41 |
53 | EE | Sheng Sun, Yi Han, Xinyu Guo, Kian Haur Chong, Larry McMurchie, Carl Sechen: 409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS. ISVLSI 2005: 52-58 |
52 | EE | Miodrag Vujkovic, David Wadkins, Carl Sechen: Efficient Post-layout Power-Delay Curve Generation. PATMOS 2005: 393-403 |
2004 | ||
51 | EE | Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen: Efficient timing closure without timing driven placement and routing. DAC 2004: 268-273 |
2003 | ||
50 | EE | Carl Sechen, Barbara Chappel, Jim Hogan, Andrew Moore, Tadahiko Nakamura, Gregory A. Northrop, Anjaneya Thakar: Libraries: lifejacket or straitjacket. DAC 2003: 642-643 |
49 | EE | Su Kio, Kian Haur Chong, Carl Sechen: A low power delayed-clocks generation and distribution system. ISCAS (5) 2003: 445-448 |
48 | EE | Jovanka Ciric, Carl Sechen: Efficient canonical form for Boolean matching of complex functions in large libraries. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 535-544 (2003) |
2002 | ||
47 | EE | Miodrag Vujkovic, Carl Sechen: Optimized power-delay curve generation for standard cell ICs. ICCAD 2002: 387-394 |
46 | EE | Hiran Tennakoon, Carl Sechen: Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. ICCAD 2002: 395-402 |
45 | EE | Larry McMurchie, Carl Sechen: WTA: waveform-based timing analysis for deep submicron circuits. ICCAD 2002: 625-631 |
44 | Miodrag Vujkovic, Carl Sechen: Optimized Power-Delay Curve Generation for Standard Cell ICs. IWLS 2002: 413-418 | |
43 | EE | G. N. Hoyer, Gin Yee, Carl Sechen: Locally clocked pipelines and dynamic logic. IEEE Trans. VLSI Syst. 10(1): 58-62 (2002) |
2001 | ||
42 | EE | Sheng Sun, Larry McMurchie, Carl Sechen: A High-Performance 64-bit Adder Implemented in Output Prediction Logic. ARVLSI 2001: 213-223 |
41 | EE | Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen: Panel: (When) Will FPGAs Kill ASICs? DAC 2001: 321-322 |
40 | EE | Tatjana Serdar, Carl Sechen: Automatic datapath tile placement and routing. DATE 2001: 552-559 |
39 | EE | Jovanka Ciric, Carl Sechen: Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries. ICCAD 2001: 610-617 |
38 | EE | Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen: Timing- and crosstalk-driven area routing. IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 528-544 (2001) |
2000 | ||
37 | EE | Jovanka Ciric, Gin Yee, Carl Sechen: Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. DATE 2000: 277-282 |
36 | EE | Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen: Output Prediction Logic: A High-Performance CMOS Design Technique. ICCD 2000: 247- |
35 | EE | Gin Yee, Tyler Thorp, Ron Christopherson, Ban P. Wang, Carl Sechen: An Automated Shielding Algorithm and Tool For Dynamic Circuits. ISQED 2000: 369-374 |
34 | EE | Gin Yee, Carl Sechen: Clock-delayed domino for dynamic circuit design. IEEE Trans. VLSI Syst. 8(4): 425-430 (2000) |
1999 | ||
33 | EE | Tatjana Serdar, Carl Sechen: AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths. ICCAD 1999: 91-97 |
32 | EE | Tyler Thorp, Gin Yee, Carl Sechen: Design and Synthesis of Monotonic Circuits. ICCD 1999: 569-572 |
31 | EE | Le-Chin Eugene Liu, Carl Sechen: Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic. IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1442-1451 (1999) |
30 | EE | Le-Chin Eugene Liu, Carl Sechen: Multilayer pin assignment for macro cell circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1452-1461 (1999) |
29 | EE | Hsiao-Ping Tseng, Carl Sechen: A gridless multilayer router for standard cell circuits using CTMcells. IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1462-1479 (1999) |
1998 | ||
28 | EE | Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen: Timing and Crosstalk Driven Area Routing. DAC 1998: 378-381 |
27 | EE | Tyler Thorp, Gin Yee, Carl Sechen: Domino logic synthesis using complex static gates. ICCAD 1998: 242-247 |
26 | EE | Le-Chin Eugene Liu, Hsiao-Ping Tseng, Carl Sechen: Chip-level area routing. ISPD 1998: 197-204 |
1997 | ||
25 | EE | Martin Lefebvre, David Marple, Carl Sechen: The Future of Custom Cell Generation in Physical Synthesis. DAC 1997: 446-451 |
24 | EE | Le-Chin Eugene Liu, Carl Sechen: Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic. ED&TC 1997: 311-318 |
23 | EE | Hsiao-Ping Tseng, Carl Sechen: A gridless multi-layer router for standard cell circuits using CTM cells. ED&TC 1997: 319-326 |
22 | EE | Qicheng Yu, Carl Sechen: Efficient approximation of symbolic network functions using matroid intersection algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1073-1081 (1997) |
21 | EE | Wern-Jieh Sun, Carl Sechen: A parallel standard cell placement algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1342-1357 (1997) |
1996 | ||
20 | EE | Gin Yee, Carl Sechen: Clock-Delayed Domino for Adder and Combinational Logic Desig. ICCD 1996: 332- |
19 | EE | Bingzhong Guan, Carl Sechen: Large Standard Cell Libraries and Their Impact on Layout Area and Circuit Performanc. ICCD 1996: 378-383 |
1995 | ||
18 | EE | Ted Stanion, Carl Sechen: Quasi-algebraic decompositions of switching functions. ARVLSI 1995: 358-367 |
17 | EE | William Swartz, Carl Sechen: Timing Driven Placement for Large Standard Cell Circuits. DAC 1995: 211-215 |
16 | EE | Ted Stanion, Carl Sechen: A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis. DAC 1995: 60-64 |
15 | EE | Kalapi Roy-Neogi, Carl Sechen: Multiple FPGA Partitioning with Performance Optimization. FPGA 1995: 146-152 |
14 | Jer-Jaw Hsu, Carl Sechen: Accurate Extraction of Simplified Symbolic Pole/Zero Expressions for Large Analog IC's. ISCAS 1995: 2083-2087 | |
13 | Qicheng Yu, Carl Sechen: Efficient Approximation of Symbolic Network Function Using Matroid Intersection Algorithms. ISCAS 1995: 2088-2091 | |
12 | EE | Ted Stanion, Debashis Bhattacharya, Carl Sechen: An efficient method for generating exhaustive test sets. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1516-1525 (1995) |
11 | EE | Wern-Jieh Sun, Carl Sechen: Efficient and effective placement for very large circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 349-359 (1995) |
1994 | ||
10 | EE | Wern-Jieh Sun, Carl Sechen: A loosely coupled parallel algorithm for standard cell placement. ICCAD 1994: 137-144 |
9 | EE | Qicheng Yu, Carl Sechen: Approximate symbolic analysis of large analog integrated circuits. ICCAD 1994: 664-671 |
8 | Kalapi Roy-Neogi, Bingzhong Guan, Carl Sechen: A Sea-of-Gates Style FPGA Placement Algorithm. VLSI Design 1994: 221-224 | |
7 | EE | Ted Stanion, Carl Sechen: Boolean division and factorization using binary decision diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 13(9): 1179-1184 (1994) |
1993 | ||
6 | EE | Wern-Jieh Sun, Carl Sechen: Efficient and effective placement for very large circuits. ICCAD 1993: 170-177 |
5 | EE | William Swartz, Carl Sechen: A new generalized row-based global router. ICCAD 1993: 491-498 |
4 | EE | Ted Stanion, Carl Sechen: Maximum projections of don't care conditions in a Boolean network. ICCAD 1993: 674-679 |
1990 | ||
3 | William Swartz, Carl Sechen: New Algorithms for the Placement and Routing of Macro Cells. ICCAD 1990: 336-339 | |
1988 | ||
2 | EE | Carl Sechen: Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing. DAC 1988: 73-80 |
1986 | ||
1 | EE | Carl Sechen, Alberto L. Sangiovanni-Vincentelli: TimberWolf3.2: a new standard cell placement and global routing package. DAC 1986: 432-439 |