| 2008 |
|---|
| 22 | EE | Kok-Leong Chang,
Bah-Hwee Gwee,
Yuanjin Zheng:
A semi-custom memory design for an asynchronous 8051 microcontroller.
ISCAS 2008: 3398-3401 |
| 21 | EE | Kok-Leong Chang,
Yao Zhu,
Bah-Hwee Gwee:
De-synchronization of a point-of-sales digital-logic controller.
ISCAS 2008: 3402-3405 |
| 20 | EE | Chong-Fatt Law,
Bah-Hwee Gwee,
Joseph Sylvester Chang:
Asynchronous Control Network Optimization Using Fast Minimum-Cycle-Time Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 985-998 (2008) |
| 2007 |
|---|
| 19 | EE | Kwen-Siong Chong,
Bah-Hwee Gwee,
Joseph Sylvester Chang:
A Low Energy FFT/IFFT Processor for Hearing Aids.
ISCAS 2007: 1169-1172 |
| 18 | EE | Kok-Leong Chang,
Bah-Hwee Gwee,
Yuanjin Zheng:
An Asynchronous Dual-Rail Multiplier based on Energy-Efficient STFB Templates.
ISCAS 2007: 3267-3270 |
| 17 | EE | Kunal Mukherjee,
Bah-Hwee Gwee:
A 32-point FFT based Noise Reduction Algorithm for Single Channel Speech Signals.
ISCAS 2007: 3928-3931 |
| 2006 |
|---|
| 16 | EE | Kok-Leong Chang,
Bah-Hwee Gwee:
A low-energy low-voltage asynchronous 8051 microcontroller core.
ISCAS 2006 |
| 15 | EE | Victor Adrian,
Bah-Hwee Gwee,
Joseph Sylvester Chang:
An acoustic noise suppression system with reduced musical artifacts.
ISCAS 2006 |
| 2005 |
|---|
| 14 | EE | Kwen-Siong Chong,
Bah-Hwee Gwee,
Joseph Sylvester Chang:
Low-voltage micropower multipliers with reduced spurious switching.
ISCAS (4) 2005: 4078-4081 |
| 13 | EE | Victor Adrian,
Bah-Hwee Gwee,
Joseph Sylvester Chang:
A combined interpolatorless interpolation and high accuracy sampling process for digital class D amplifiers.
ISCAS (6) 2005: 5405-5408 |
| 12 | EE | Kwen-Siong Chong,
Bah-Hwee Gwee,
Joseph Sylvester Chang:
A micropower low-voltage multiplier with reduced spurious switching.
IEEE Trans. VLSI Syst. 13(2): 255-265 (2005) |
| 11 | EE | Bah-Hwee Gwee,
Meng-Hiot Lim:
An evolution search algorithm for solving N-queen problems.
IJCAT 24(1): 43-48 (2005) |
| 2004 |
|---|
| 10 | | Kwen-Siong Chong,
Bah-Hwee Gwee,
Joseph Sylvester Chang:
A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders.
ISCAS (2) 2004: 437-440 |
| 9 | EE | Victor Adrian,
Bah-Hwee Gwee,
Joseph Sylvester Chang:
A novel combined first and second order Lagrange interpolation sampling process for a digital class D amplifier.
ISCAS (3) 2004: 233-260 |
| 2003 |
|---|
| 8 | | Bah-Hwee Gwee,
Joseph Sylvester Chang:
A Hybrid Genetic Hill-climbing Algorithm for Four-Coloring Map Problems.
HIS 2003: 252-261 |
| 7 | EE | Bah-Hwee Gwee,
Joseph Sylvester Chang,
Victor Adrian,
H. Amir:
A novel sampling process and pulse generator for a low distortion digital pulse-width modulator for digital class D amplifiers.
ISCAS (4) 2003: 504-507 |
| 6 | EE | Chien-Chung Chua,
Bah-Hwee Gwee,
Joseph Sylvester Chang:
A low-voltage micropower asynchronous multiplier for a multiplierless FIR filter.
ISCAS (5) 2003: 381-384 |
| 5 | | Khia-Ho Chang,
Bah-Hwee Gwee,
Joseph Sylvester Chang:
A Low Voltage Micropower 16-Word by 16-Bit 3-Port Asynchronous Register File.
VLSI 2003: 166-172 |
| 2002 |
|---|
| 4 | EE | Kwen-Siong Chong,
Bah-Hwee Gwee,
Joseph Sylvester Chang:
Low-voltage micropower asynchronous multiplier for hearing instruments.
ISCAS (1) 2002: 865-868 |
| 3 | EE | Kwen-Siong Chong,
Bah-Hwee Gwee,
Joseph Sylvester Chang:
Low-voltage asynchronous adders for low power and high speed applications.
ISCAS (1) 2002: 873-876 |
| 2001 |
|---|
| 2 | EE | Joseph Sylvester Chang,
Bah-Hwee Gwee,
Yong Seng Lon,
Meng Tong Tan:
A novel low-power low-voltage Class D amplifier with feedback for improving THD, power efficiency and gain linearity.
ISCAS (1) 2001: 635-638 |
| 1 | EE | Huiyun Li,
Bah-Hwee Gwee,
Joseph Sylvester Chang:
A digital Class D amplifier design embodying a novel sampling process and pulse generator.
ISCAS (4) 2001: 826-829 |
