| 2008 |
|---|
| 11 | EE | Hua Xiang,
Liang Deng,
Ruchir Puri,
Kai-Yuan Chao,
Martin D. F. Wong:
Fast Dummy-Fill Density Analysis With Coupling Constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 633-642 (2008) |
| 2007 |
|---|
| 10 | EE | Liang Deng,
Martin D. F. Wong,
Kai-Yuan Chao,
Hua Xiang:
Coupling-aware Dummy Metal Insertion for Lithography.
ASP-DAC 2007: 13-18 |
| 9 | EE | David M. Pawlowski,
Liang Deng,
Martin D. F. Wong:
Fast and Accurate OPC for Standard-Cell Layouts.
ASP-DAC 2007: 7-12 |
| 8 | EE | Hua Xiang,
Liang Deng,
Ruchir Puri,
Kai-Yuan Chao,
Martin D. F. Wong:
Dummy fill density analysis with coupling constraints.
ISPD 2007: 3-10 |
| 7 | EE | Hua Xiang,
Liang Deng,
Li-Da Huang,
Martin D. F. Wong:
OPC-Friendly Bus Driven Floorplanning.
ISQED 2007: 847-852 |
| 2006 |
|---|
| 6 | EE | Liang Deng,
Martin D. F. Wong:
An exact algorithm for the statistical shortest path problem.
ASP-DAC 2006: 965-970 |
| 5 | EE | Lei Cheng,
Liang Deng,
Deming Chen,
Martin D. F. Wong:
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction.
DAC 2006: 117-120 |
| 2005 |
|---|
| 4 | EE | Liang Deng,
Martin D. F. Wong:
Energy optimization in memory address bus structure for application-specific systems.
ACM Great Lakes Symposium on VLSI 2005: 232-237 |
| 3 | EE | Lei Cheng,
Liang Deng,
Martin D. F. Wong:
Floorplanning for 3-D VLSI design.
ASP-DAC 2005: 405-411 |
| 2 | | Liang Deng,
Martin D. F. Wong:
Buffer insertion under process variations for delay minimization.
ICCAD 2005: 317-321 |
| 2004 |
|---|
| 1 | EE | Liang Deng,
Martin D. F. Wong:
Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus.
DATE 2004: 1104-1109 |
