2009 |
38 | EE | Youngsoo Shin,
Seungwhun Paik,
Hyung-Ock Kim:
Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 327-339 (2009) |
37 | EE | Eunjoo Choi,
Changsik Shin,
Youngsoo Shin:
ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 451-456 (2009) |
2008 |
36 | EE | Jinseob Jeong,
Seungwhun Paik,
Youngsoo Shin:
Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation.
ASP-DAC 2008: 629-634 |
35 | EE | Seungwhun Paik,
Youngsoo Shin:
Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements.
DAC 2008: 600-605 |
34 | EE | Hyein Lee,
Seungwhun Paik,
Youngsoo Shin:
Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits.
ICCAD 2008: 224-229 |
33 | EE | Eunjoo Choi,
Youngsoo Shin:
3-D thermal simulation with dynamic power profiles.
ISCAS 2008: 2765-2768 |
32 | EE | Eunjoo Choi,
Changsik Shin,
Taewhan Kim,
Youngsoo Shin:
Power-gating-aware high-level synthesis.
ISLPED 2008: 39-44 |
31 | EE | Jun Seomun,
Jae-Hyun Kim,
Youngsoo Shin:
Skewed Flip-Flop and Mixed-Vt Gates for Minimizing Leakage in Sequential Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 1956-1968 (2008) |
2007 |
30 | EE | Youngsoo Shin,
Sewan Heo,
Hyung-Ock Kim,
Jung Yun Choi:
Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.
ASP-DAC 2007: 654-659 |
29 | EE | Jun Seomun,
Jaehyun Kim,
Youngsoo Shin:
Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits.
DAC 2007: 103-106 |
28 | EE | Jaehyun Kim,
Youngsoo Shin:
Minimizing leakage power in sequential circuits by using mixed Vt flip-flops.
ICCAD 2007: 797-802 |
27 | EE | Youngsoo Shin,
Hyung-Ock Kim:
Cell-Based Semicustom Design of Zigzag Power Gating Circuits.
ISQED 2007: 527-532 |
26 | EE | Byunghee Choi,
Youngsoo Shin:
Lookup Table-Based Adaptive Body Biasing of Multiple Macros.
ISQED 2007: 533-538 |
25 | EE | Youngsoo Shin,
Sewan Heo,
Hyung-Ock Kim,
Jung Yun Choi:
Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.
IEEE Trans. VLSI Syst. 15(7): 758-766 (2007) |
2006 |
24 | EE | Hyung-Ock Kim,
Youngsoo Shin:
Analysis and optimization of gate leakage current of power gating circuits.
ASP-DAC 2006: 565-569 |
23 | EE | Hyung-Ock Kim,
Youngsoo Shin,
Hyuk Kim,
Iksoo Eo:
Physical design methodology of power gating circuits for standard-cell-based design.
DAC 2006: 109-112 |
22 | EE | Youngsoo Shin,
Junghyup Lee:
Power Analysis of VLSI Interconnect with RLC Tree Models and Model Reduction.
Journal of Circuits, Systems, and Computers 15(3): 399-408 (2006) |
2005 |
21 | EE | Hyung-Ock Kim,
Youngsoo Shin:
Power-aware slack distribution for hierarchical VLSI design.
ISCAS (4) 2005: 4150-4153 |
20 | EE | Youngsoo Shin,
Hyung-Ock Kim:
Analysis of power consumption in VLSI global interconnects.
ISCAS (5) 2005: 4713-4716 |
19 | EE | Subhrajit Bhattacharya,
John A. Darringer,
Daniel L. Ostapko,
Youngsoo Shin:
A Mask Reuse Methodology for Reducing System-on-a-Chip Cost.
ISQED 2005: 482-487 |
18 | EE | Hiroshi Kawaguchi,
Youngsoo Shin,
Takayasu Sakurai:
/spl mu/ITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications.
IEEE Transactions on Multimedia 7(1): 67-74 (2005) |
2004 |
17 | EE | Jingcao Hu,
Youngsoo Shin,
Nagu R. Dhanwada,
Radu Marculescu:
Architecting voltage islands in core-based system-on-a-chip designs.
ISLPED 2004: 180-185 |
2003 |
16 | EE | Reinaldo A. Bergamaschi,
Youngsoo Shin,
Nagu R. Dhanwada,
Subhrajit Bhattacharya,
William E. Dougherty,
Indira Nair,
John A. Darringer,
Sarala Paliwal:
SEAS: a system for early analysis of SoCs.
CODES+ISSS 2003: 150-155 |
2002 |
15 | EE | John A. Darringer,
Reinaldo A. Bergamaschi,
Subhrajit Bhattacharya,
Daniel Brand,
Andreas Herkersdorf,
Joseph K. Morrell,
Indira Nair,
Patricia Sagmeister,
Youngsoo Shin:
Early analysis tools for system-on-a-chip design.
IBM Journal of Research and Development 46(6): 691-708 (2002) |
2001 |
14 | EE | Youngsoo Shin,
Takayasu Sakurai:
Coupling-Driven Bus Design for Low-Power Application-Specific Systems.
DAC 2001: 750-753 |
13 | EE | Youngsoo Shin,
Takayasu Sakurai:
Estimation of power distribution in VLSI interconnects.
ISLPED 2001: 370-375 |
12 | EE | Youngsoo Shin,
Soo-Ik Chae,
Kiyoung Choi:
Partial bus-invert coding for power optimization of application-specific systems.
IEEE Trans. VLSI Syst. 9(2): 377-383 (2001) |
11 | EE | Youngsoo Shin,
Kiyoung Choi,
Young-Hoon Chang:
Narrow bus encoding for low-power DSP systems.
IEEE Trans. VLSI Syst. 9(5): 656-660 (2001) |
2000 |
10 | EE | Youngsoo Shin,
Kiyoung Choi:
Narrow bus encoding for low power systems.
ASP-DAC 2000: 217-220 |
9 | EE | Youngsoo Shin,
Daehong Kim,
Kiyoung Choi:
Schedulability-driven performance analysis of multiple mode embedded real-time systems.
DAC 2000: 495-500 |
8 | | Youngsoo Shin,
Kiyoung Choi,
Takayasu Sakurai:
Power Optimization of Real-Time Embedded Systems on Variable Speed Processors.
ICCAD 2000: 365-368 |
1999 |
7 | EE | Youngsoo Shin,
Kiyoung Choi:
Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems.
DAC 1999: 134-139 |
1998 |
6 | EE | Youngsoo Shin,
Kiyoung Choi:
Rate Assignment for Embedded Reactive Real-Time Systems.
EUROMICRO 1998: 10237- |
5 | EE | Youngsoo Shin,
Soo-Ik Chae,
Kiyoung Choi:
Partial bus-invert coding for power optimization of system level bus.
ISLPED 1998: 127-129 |
1997 |
4 | EE | Youngsoo Shin,
Kiyoung Choi:
Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign.
CODES 1997: 3-8 |
1996 |
3 | EE | Youngsoo Shin,
Kiyoung Choi:
Software synthesis through task decomposition by dependency analysis.
ICCAD 1996: 98-104 |
1995 |
2 | EE | Yongjoo Kim,
Kyuseok Kim,
Youngsoo Shin,
Taekyoon Ahn,
Wonyong Sung,
Kiyoung Choi,
Soonhoi Ha:
An integrated hardware-software cosimulation environment for heterogeneous systems prototyping.
ASP-DAC 1995 |
1 | | Yongjoo Kim,
Youngsoo Shin,
Kyuseok Kim,
Jae-Hee Won,
Kiyoung Choi:
Efficient Prototyping System Based on Incremental Design and Module-by-Module Verification.
ISCAS 1995: 924-927 |