| |
| 2008 | ||
|---|---|---|
| 3 | EE | Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi: A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1535-1544 (2008) |
| 2007 | ||
| 2 | EE | Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara: A DFT Method for Time Expansion Model at Register Transfer Level. DAC 2007: 682-687 |
| 2005 | ||
| 1 | EE | Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara: A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. Asian Test Symposium 2005: 306-311 |
| 1 | Hideo Fujiwara | [1] [2] [3] |
| 2 | Satoshi Ohtake | [1] |
| 3 | Chia Yee Ooi | [3] |
| 4 | Tomokazu Yoneda | [1] [2] [3] |