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Adrian M. Ionescu

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2008
11EEYogesh Singh Chauhan, D. Tsamados, Nicolas Abelé, C. Eggimann, Michel J. Declercq, Adrian M. Ionescu: Compact Modeling of Suspended Gate FET. VLSI Design 2008: 119-124
10EENicolas Abelé, D. Grogg, C. Hibert, F. Casset, Pascal Ancey, Adrian M. Ionescu: 0-level Vacuum Packaging RT Process for MEMS Resonators CoRR abs/0802.3093: (2008)
9EEM. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli: Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2053-2067 (2008)
2007
8EEM. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli: Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays. ICCAD 2007: 765-772
7EEYogesh Singh Chauhan, Francois Krummenacher, Renaud Gillon, Benoit Bakeroot, Michel J. Declercq, Adrian M. Ionescu: A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling. VLSI Design 2007: 177-182
2005
6EESorin Cotofana, Alexandre Schmid, Yusuf Leblebici, Adrian M. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, A. Rubio: CONAN - A Design Exploration Framework for Reliable Nano-Electronics. ASAP 2005: 260-267
2004
5EEAnirban Basu, Sheng-Chih Lin, Christoph Wasshuber, Adrian M. Ionescu, Kaustav Banerjee: A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array. ISQED 2004: 259-264
2003
4EESantanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian M. Ionescu: A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits. ICCAD 2003: 497-503
2002
3EEAdrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier: Few electron devices: towards hybrid CMOS-SET integrated circuits. DAC 2002: 88-93
2EESantanu Mahapatra, Adrian M. Ionescu, Kaustav Banerjee, Michel J. Declercq: A SET quantizer circuit aiming at digital communication system. ISCAS (5) 2002: 860-863
1EEAdrian M. Ionescu, V. Pott, R. Fritschi, Kaustav Banerjee, Michel J. Declercq, P. Renaud, C. Hibert, Philippe Flückiger, G. A. Racine: Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate Architecture. ISQED 2002: 496-501

Coauthor Index

1Nicolas Abelé [10] [11]
2Pascal Ancey [10]
3David Atienza [8] [9]
4Benoit Bakeroot [7]
5Kaustav Banerjee [1] [2] [3] [4] [5]
6Anirban Basu [5]
7Didier Bouvet [8] [9]
8F. Casset [10]
9Yogesh Singh Chauhan [7] [11]
10Sorin Cotofana (Sorin Dan Cotofana) [6]
11Michel J. Declercq [1] [2] [3] [7] [11]
12C. Eggimann [11]
13Philippe Flückiger [1]
14R. Fritschi [1]
15Jacques Gautier [3]
16Renaud Gillon [7]
17Manfred Glesner [6]
18D. Grogg [10]
19C. Hibert [1] [10]
20M. Haykel Ben Jamaa [8] [9]
21Francois Krummenacher [7]
22Yusuf Leblebici [6] [8] [9]
23Sheng-Chih Lin [5]
24Santanu Mahapatra [2] [3] [4]
25Giovanni De Micheli [8] [9]
26Kirsten E. Moselund [8] [9]
27Florent Pegeon [4]
28V. Pott [1]
29G. A. Racine [1]
30P. Renaud [1]
31A. Rubio [6]
32Alexandre Schmid [6]
33Oliver Soffke [6]
34D. Tsamados [11]
35Christoph Wasshuber [5]
36Peter Zipf [6]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)