2008 |
11 | EE | Yogesh Singh Chauhan,
D. Tsamados,
Nicolas Abelé,
C. Eggimann,
Michel J. Declercq,
Adrian M. Ionescu:
Compact Modeling of Suspended Gate FET.
VLSI Design 2008: 119-124 |
10 | EE | Nicolas Abelé,
D. Grogg,
C. Hibert,
F. Casset,
Pascal Ancey,
Adrian M. Ionescu:
0-level Vacuum Packaging RT Process for MEMS Resonators
CoRR abs/0802.3093: (2008) |
9 | EE | M. Haykel Ben Jamaa,
Kirsten E. Moselund,
David Atienza,
Didier Bouvet,
Adrian M. Ionescu,
Yusuf Leblebici,
Giovanni De Micheli:
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2053-2067 (2008) |
2007 |
8 | EE | M. Haykel Ben Jamaa,
Kirsten E. Moselund,
David Atienza,
Didier Bouvet,
Adrian M. Ionescu,
Yusuf Leblebici,
Giovanni De Micheli:
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays.
ICCAD 2007: 765-772 |
7 | EE | Yogesh Singh Chauhan,
Francois Krummenacher,
Renaud Gillon,
Benoit Bakeroot,
Michel J. Declercq,
Adrian M. Ionescu:
A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling.
VLSI Design 2007: 177-182 |
2005 |
6 | EE | Sorin Cotofana,
Alexandre Schmid,
Yusuf Leblebici,
Adrian M. Ionescu,
Oliver Soffke,
Peter Zipf,
Manfred Glesner,
A. Rubio:
CONAN - A Design Exploration Framework for Reliable Nano-Electronics.
ASAP 2005: 260-267 |
2004 |
5 | EE | Anirban Basu,
Sheng-Chih Lin,
Christoph Wasshuber,
Adrian M. Ionescu,
Kaustav Banerjee:
A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array.
ISQED 2004: 259-264 |
2003 |
4 | EE | Santanu Mahapatra,
Kaustav Banerjee,
Florent Pegeon,
Adrian M. Ionescu:
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits.
ICCAD 2003: 497-503 |
2002 |
3 | EE | Adrian M. Ionescu,
Michel J. Declercq,
Santanu Mahapatra,
Kaustav Banerjee,
Jacques Gautier:
Few electron devices: towards hybrid CMOS-SET integrated circuits.
DAC 2002: 88-93 |
2 | EE | Santanu Mahapatra,
Adrian M. Ionescu,
Kaustav Banerjee,
Michel J. Declercq:
A SET quantizer circuit aiming at digital communication system.
ISCAS (5) 2002: 860-863 |
1 | EE | Adrian M. Ionescu,
V. Pott,
R. Fritschi,
Kaustav Banerjee,
Michel J. Declercq,
P. Renaud,
C. Hibert,
Philippe Flückiger,
G. A. Racine:
Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate Architecture.
ISQED 2002: 496-501 |