Daniel Große

2009
32	EE	Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler: Contradictory antecedent debugging in bounded model checking. ACM Great Lakes Symposium on VLSI 2009: 173-176
31	EE	Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler: Reversible Logic Synthesis with Output Permutation. VLSI Design 2009: 189-194
2008
30	EE	Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große: Quantified Synthesis of Reversible Logic. DATE 2008: 1015-1020
29	EE	Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler: Contradiction Analysis for Constraint-based Random Simulation. FDL 2008: 130-135
28	EE	Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. ISMVL 2008: 214-219
27	EE	Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler: RevLib: An Online Resource for Reversible Functions and Reversible Circuits. ISMVL 2008: 220-225
26	EE	Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler: Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. ISVLSI 2008: 411-416
25	EE	Daniel Große, Ulrich Kühne, Rolf Drechsler: Analyzing Functional Coverage in Bounded Model Checking. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1305-1314 (2008)
2007
24	EE	Daniel Große, Rüdiger Ebendt, Rolf Drechsler: Improvements for constraint solving in the systemc verification library. ACM Great Lakes Symposium on VLSI 2007: 493-496
23	EE	Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler: Exact sat-based toffoli network synthesis. ACM Great Lakes Symposium on VLSI 2007: 96-101
22	EE	Daniel Große, Ulrich Kühne, Rolf Drechsler: Estimating functional coverage in bounded model checking. DATE 2007: 1176-1181
21	EE	Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler: Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques. FDL 2007: 146-151
20	EE	Robert Wille, Daniel Große: Fast exact Toffoli network synthesis of reversible logic. ICCAD 2007: 60-64
19	EE	Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler: Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. ISMVL 2007: 50
18	EE	Ulrich Kühne, Daniel Große, Rolf Drechsler: Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. ISVLSI 2007: 165-170
17	EE	Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler: SWORD: A SAT like prover using word level information. VLSI-SoC 2007: 88-93
2006
16	EE	Daniel Große, Ulrich Kühne, Rolf Drechsler: HW/SW co-verification of embedded systems using bounded model checking. ACM Great Lakes Symposium on VLSI 2006: 43-48
15	EE	Görschwin Fey, Daniel Große, Rolf Drechsler: Avoiding false negatives in formal verification for protocol-driven blocks. DATE 2006: 1225-1226
2005
14	EE	Daniel Große, Rolf Drechsler: Acceleration of SAT-Based Iterative Property Checking. CHARME 2005: 349-353
13		Daniel Große, Ulrich Kühne, Rolf Drechsler: Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors. GI Jahrestagung (1) 2005: 308-312
12	EE	Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große: SyCE: An Integrated Environment for System Design in SystemC. IEEE International Workshop on Rapid System Prototyping 2005: 258-260
11	EE	Daniel Große, Rolf Drechsler: CheckSyC: an efficient property checker for RTL SystemC designs. ISCAS (4) 2005: 4167-4170
10	EE	Daniel Große, Ulrich Kühne, Rolf Drechsler: HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. MTV 2005: 133-137
2004
9	EE	Daniel Große, Rolf Drechsler: Checkers for SystemC designs. MEMOCODE 2004: 171-178
2003
8	EE	Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst: Efficient Automatic Visualization of SystemC Designs. FDL 2003: 646-658
7	EE	Daniel Große, Rolf Drechsler: Formal verification of LTL formulas for SystemC designs. ISCAS (5) 2003: 245-248
6	EE	Daniel Große, Görschwin Fey, Rolf Drechsler: Modeling Multi-Valued Circuits in SystemC. ISMVL 2003: 281-286
5		Daniel Große, Rolf Drechsler: Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC. it - Information Technology 45(4): 219-226 (2003)
2002
4	EE	Rolf Drechsler, Daniel Große: Reachability Analysis for Formal Verification of SystemC. DSD 2002: 337-340
3		Frank Schmiedle, Nicole Drechsler, Daniel Große, Rolf Drechsler: Heuristic Learning Based on Genetic Programming. Genetic Programming and Evolvable Machines 3(4): 363-388 (2002)
2001
2	EE	Nicole Drechsler, Frank Schmiedle, Daniel Große, Rolf Drechsler: Heuristic Learning Based on Genetic Programming. EuroGP 2001: 1-10
1	EE	Frank Schmiedle, Daniel Große, Rolf Drechsler, Bernd Becker: Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics. Fuzzy Days 2001: 479-491

Coauthor Index

1	Mahsan Amoui	[19]
2	Gerhard Angst	[8]
3	Bernd Becker	[1]
4	Xiaobo Chen	[23]
5	Nicole Drechsler	[2] [3]
6	Rolf Drechsler	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [21] [22] [23] [24] [25] [26] [27] [28] [29] [31] [32]
7	Gerhard W. Dueck	[23] [27] [28] [30] [31]
8	Rüdiger Ebendt	[24]
9	Stephan Eggersglüß	[17]
10	Görschwin Fey	[6] [12] [15] [17]
11	Christian Genz	[12]
12	Wolfgang Klingauf	[21]
13	Ulrich Kühne	[10] [13] [16] [18] [22] [25] [32]
14	Hoang M. Le	[30]
15	Lothar Linhard	[8]
16	Hernan Peraza	[21]
17	Frank Schmiedle	[1] [2] [3]
18	Robert Siegmund	[29]
19	Mathias Soeken	[26]
20	Lisa Teuber	[27]
21	Mitchell A. Thornton (Mitchell Aaron Thornton)	[19]
22	Robert Wille	[17] [20] [26] [27] [28] [29] [30] [31] [32]