| |
| 2008 | ||
|---|---|---|
| 5 | EE | Aijiao Cui, Chip-Hong Chang: Intellectual property authentication by watermarking scan chain in design-for-testability flow. ISCAS 2008: 2645-2648 |
| 4 | EE | Aijiao Cui, Chip-Hong Chang, Sofiène Tahar: IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1565-1570 (2008) |
| 2007 | ||
| 3 | EE | Aijiao Cui, Chip-Hong Chang: Watermarking for IP Protection through Template Substitution at Logic Synthesis Level. ISCAS 2007: 3687-3690 |
| 2006 | ||
| 2 | EE | Aijiao Cui, Chip-Hong Chang: Kernel Extraction for Watermarking Combinational Logic Networks. APCCAS 2006: 1023-1026 |
| 1 | EE | Aijiao Cui, Chip-Hong Chang: Stego-signature at logic synthesis level for digital design IP protection. ISCAS 2006 |
| 1 | Chip-Hong Chang | [1] [2] [3] [4] [5] |
| 2 | Sofiène Tahar | [4] |