Prabhat Mishra

2009
38	EE	Chetan Murthy, Prabhat Mishra: Bitmask-based control word compression for NISC architectures. ACM Great Lakes Symposium on VLSI 2009: 321-326
37	EE	Xiaoke Qin, Prabhat Mishra: Efficient Placement of Compressed Code for Parallel Decompression. VLSI Design 2009: 335-340
36	EE	Weixun Wang, Prabhat Mishra, Ann Gordon-Ross: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems. VLSI Design 2009: 547-552
35	EE	Prabhat Mishra, Mingsong Chen: Efficient Techniques for Directed Test Generation Using Incremental Satisfiability. VLSI Design 2009: 65-70
34	EE	Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt: Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation. ACM Trans. Embedded Comput. Syst. 8(3): (2009)
2008
33	EE	Mingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita: Coverage-driven automatic test generation for uml activity diagrams. ACM Great Lakes Symposium on VLSI 2008: 139-142
32	EE	Kanad Basu, Prabhat Mishra: A novel test-data compression technique using application-aware bitmask and dictionary selection methods. ACM Great Lakes Symposium on VLSI 2008: 83-88
31	EE	Heon-Mo Koo, Prabhat Mishra: Specification-based compaction of directed tests for functional validation of pipelined processors. CODES+ISSS 2008: 137-142
30	EE	Prabhat Mishra, Nikil Dutt: Specification-driven directed test generation for validation of pipelined processors. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
29	EE	Seok-Won Seong, Prabhat Mishra: Bitmask-Based Code Compression for Embedded Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 673-685 (2008)
2007
28	EE	Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra, Xu Cheng: A Retargetable Software Timing Analyzer Using Architecture Description Language. ASP-DAC 2007: 396-401
27	EE	Seok-Won Seong, Prabhat Mishra: An efficient code compression technique using application-aware bitmask and dictionary selection methods. DATE 2007: 582-587
2006
26	EE	Heon-Mo Koo, Prabhat Mishra: Test generation using SAT-based bounded model checking for validation of pipelined processors. ACM Great Lakes Symposium on VLSI 2006: 362-365
25	EE	Heon-Mo Koo, Prabhat Mishra: Functional test generation using property decompositions for validation of pipelined processors. DATE 2006: 1240-1245
24	EE	Seok-Won Seong, Prabhat Mishra: A bitmask-based code compression technique for embedded systems. ICCAD 2006: 251-254
23	EE	Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir: Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. MTV 2006: 33-36
22	EE	Prabhat Mishra, Aviral Shrivastava, Nikil Dutt: Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs. ACM Trans. Design Autom. Electr. Syst. 11(3): 626-658 (2006)
21	EE	Mehrdad Reshadi, Nikil Dutt, Prabhat Mishra: A retargetable framework for instruction-set architecture simulation. ACM Trans. Embedded Comput. Syst. 5(2): 431-452 (2006)
2005
20	EE	Mehrdad Reshadi, Prabhat Mishra: Memory access optimizations in instruction-set simulators. CODES+ISSS 2005: 237-242
19	EE	Prabhat Mishra, Nikil D. Dutt: Functional Coverage Driven Test Generation for Validation of Pipelined Processors. DATE 2005: 678-683
18	EE	Prabhat Mishra, Heon-Mo Koo, Zhuo Huang: Language-driven Validation of Pipelined Processors using Satisfiability Solvers. MTV 2005: 119-126
17	EE	Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir: A methodology for validation of microprocessors using symbolic simulation. IJES 1(1/2): 14-22 (2005)
2004
16	EE	Prabhat Mishra, Nikil Dutt: Graph-Based Functional Test Program Generation for Pipelined Processors. DATE 2004: 182-187
15	EE	Prabhat Mishra, Nikil D. Dutt: Functional Validation of Programmable Architectures. DSD 2004: 12-19
14	EE	Prabhat Mishra, Nikil D. Dutt, Yaron Kashai: Functional Verification of Pipelined Processors: A Case Study. MTV 2004: 79-84
13	EE	Prabhat Mishra, Arun Kejariwal, Nikil Dutt: Synthesis-driven Exploration of Pipelined Embedded Processors. VLSI Design 2004: 921-926
12	EE	Prabhat Mishra, Nikil Dutt: Modeling and validation of pipeline specifications. ACM Trans. Embedded Comput. Syst. 3(1): 114-139 (2004)
11	EE	Prabhat Mishra, Mahesh Mamidipaka, Nikil Dutt: Processor-memory coexploration using an architecture description language. ACM Trans. Embedded Comput. Syst. 3(1): 140-162 (2004)
10	EE	Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, Magdy S. Abadir: A Top-Down Methodology for Microprocessor Validation. IEEE Design & Test of Computers 21(2): 122-131 (2004)
2003
9	EE	Mehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, Nikil D. Dutt: An efficient retargetable framework for instruction-set simulation. CODES+ISSS 2003: 13-18
8	EE	Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt: Instruction set compiled simulation: a technique for fast and flexible instruction set simulation. DAC 2003: 758-763
7	EE	Prabhat Mishra, Arun Kejariwal, Nikil Dutt: Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models. IEEE International Workshop on Rapid System Prototyping 2003: 226-232
6	EE	Prabhat Mishra, Nikil D. Dutt: A Methodology for Validation of Microprocessors using Equivalence Checking. MTV 2003: 83-88
2002
5	EE	Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama: Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. DATE 2002: 36-43
4		Prabhat Mishra, Nikil D. Dutt: Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions. DIPES 2002: 81-90
3	EE	Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. VLSI Design 2002: 458-
2001
2		Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau: Functional abstraction driven design space exploration of heterogeneous programmable architectures. ISSS 2001: 256-261
1	EE	Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language. VLSI Design 2001: 70-75

Coauthor Index

1	Magdy S. Abadir	[10] [17] [23]
2	Nikhil Bansal	[9]
3	Kanad Basu	[32]
4	Jayanta Bhadra	[23]
5	Mingsong Chen	[33] [35]
6	Xu Cheng	[28]
7	Nikil D. Dutt (Nikil Dutt)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [19] [21] [22] [30] [34]
8	Ann Gordon-Ross	[36]
9	Peter Grun	[1] [3]
10	Ashok Halambi	[3]
11	Zhuo Huang	[18]
12	Dhrubajyoti Kalita	[33]
13	Yaron Kashai	[14]
14	Arun Kejariwal	[7] [13]
15	Heon-Mo Koo	[18] [23] [25] [26] [31]
16	Narayanan Krishnamurthy	[10] [17]
17	Xianfeng Li	[28]
18	Mahesh Mamidipaka	[11]
19	Tulika Mitra	[28]
20	Chetan Murthy	[38]
21	Alexandru Nicolau (Alex Nicolau)	[1] [2] [3] [5]
22	Xiaoke Qin	[37]
23	Mehrdad Reshadi	[8] [9] [20] [21] [34]
24	Abhik Roychoudhury	[28]
25	Seok-Won Seong	[24] [27] [29]
26	Aviral Shrivastava	[22]
27	Hiroyuki Tomiyama	[3] [5]
28	Weixun Wang	[36]

Colors in the list of coauthors