| 2008 |
|---|
| 10 | EE | Jimson Mathew,
Jawar Singh,
Abusaleh M. Jabir,
Mohammad Hosseinabady,
Dhiraj K. Pradhan:
Fault tolerant bit parallel finite field multipliers using LDPC codes.
ISCAS 2008: 1684-1687 |
| 9 | EE | Jimson Mathew,
Costas Argyrides,
Abusaleh M. Jabir,
Hafizur Rahaman,
Dhiraj K. Pradhan:
Single Error Correcting Finite Field Multipliers Over GF(2m).
VLSI Design 2008: 33-38 |
| 8 | EE | Jimson Mathew,
Hafizur Rahaman,
A. K. Singh,
Abusaleh M. Jabir,
Dhiraj K. Pradhan:
A Galois Field Based Logic Synthesis Approach with Testability.
VLSI Design 2008: 629-634 |
| 7 | EE | Hafizur Rahaman,
Jimson Mathew,
Dhiraj K. Pradhan,
Abusaleh M. Jabir:
C-testable bit parallel multipliers over GF(2m).
ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
| 6 | EE | Hafizur Rahaman,
Jimson Mathew,
Dhiraj K. Pradhan,
Abusaleh M. Jabir:
Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m).
IEEE Trans. Computers 57(9): 1289-1294 (2008) |
| 5 | EE | Abusaleh M. Jabir,
Dhiraj K. Pradhan,
Jimson Mathew:
GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 698-711 (2008) |
| 2007 |
|---|
| 4 | EE | Abusaleh M. Jabir,
Dhiraj K. Pradhan:
A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields.
IEEE Trans. Computers 56(8): 1119-1132 (2007) |
| 3 | EE | Abusaleh M. Jabir,
Dhiraj K. Pradhan,
T. L. Rajaprabhu,
A. K. Singh:
A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation.
IEEE Trans. Computers 56(8): 1133-1145 (2007) |
| 2006 |
|---|
| 2 | EE | Abusaleh M. Jabir,
Dhiraj K. Pradhan,
Jimson Mathew:
An efficient technique for synthesis and optimization of polynomials in GF(2m).
ICCAD 2006: 151-157 |
| 2004 |
|---|
| 1 | EE | Abusaleh M. Jabir,
Dhiraj K. Pradhan:
MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions.
DATE 2004: 1388-1389 |
