2008 |
21 | EE | Deepa Kannan,
Aviral Shrivastava,
Vipin Mohan,
Sarvesh Bhardwaj,
Sarma B. K. Vrudhula:
Temperature and Process Variations Aware Power Gating of Functional Units.
VLSI Design 2008: 515-520 |
20 | EE | Deepa Kannan,
Aviral Shrivastava,
Sarvesh Bhardwaj,
Sarma Vrudhul:
Power Reduction of Functional Units Considering Temperature and Process Variations.
VLSI Design 2008: 533-539 |
19 | EE | Sarvesh Bhardwaj,
Sarma B. K. Vrudhula,
Amit Goel:
A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1812-1825 (2008) |
18 | EE | Sarvesh Bhardwaj,
Sarma B. K. Vrudhula:
Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 445-455 (2008) |
2007 |
17 | EE | Wenping Wang,
Shengqi Yang,
Sarvesh Bhardwaj,
Rakesh Vattikonda,
Sarma B. K. Vrudhula,
Frank Liu,
Yu Cao:
The Impact of NBTI on the Performance of Combinational and Sequential Circuits.
DAC 2007: 364-369 |
16 | EE | Amit Goel,
Sarvesh Bhardwaj,
Praveen Ghanta,
Sarma B. K. Vrudhula:
Computation of Joint Timing Yield of Sequential Networks Considering Process Variations.
PATMOS 2007: 125-137 |
15 | EE | Sarvesh Bhardwaj,
Sarma B. K. Vrudhula:
A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations.
VLSI Design 2007: 589-594 |
14 | EE | Sarma B. K. Vrudhula,
Sarvesh Bhardwaj:
Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations.
VLSI Design 2007: 9 |
2006 |
13 | EE | Sarvesh Bhardwaj,
Yu Cao,
Sarma B. K. Vrudhula:
Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage.
ASP-DAC 2006: 953-958 |
12 | EE | Praveen Ghanta,
Sarma B. K. Vrudhula,
Sarvesh Bhardwaj,
Rajendran Panda:
Stochastic variational analysis of large power grids considering intra-die correlations.
DAC 2006: 211-216 |
11 | EE | Sarvesh Bhardwaj,
Sarma B. K. Vrudhula,
Praveen Ghanta,
Yu Cao:
Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits.
DAC 2006: 791-796 |
10 | EE | Sarvesh Bhardwaj,
Praveen Ghanta,
Sarma B. K. Vrudhula:
A framework for statistical timing analysis using non-linear delay and slew models.
ICCAD 2006: 225-230 |
9 | EE | Sarvesh Bhardwaj,
Yu Cao,
Sarma B. K. Vrudhula:
LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs.
ISQED 2006: 717-722 |
8 | EE | Sarvesh Bhardwaj,
Yu Cao,
Sarma B. K. Vrudhula:
Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection.
J. Low Power Electronics 2(2): 240-250 (2006) |
2005 |
7 | EE | Vineet Agarwal,
Navneeth Kankani,
Ravishankar Rao,
Sarvesh Bhardwaj,
Janet Meiling Wang:
An efficient combinationality check technique for the synthesis of cyclic combinational circuits.
ASP-DAC 2005: 212-215 |
6 | EE | Sarvesh Bhardwaj,
Sarma B. K. Vrudhula:
Leakage minimization of nano-scale circuits in the presence of systematic and random variations.
DAC 2005: 541-546 |
5 | | Sarvesh Bhardwaj,
Sarma B. K. Vrudhula:
Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs.
ICCAD 2005: 713-718 |
4 | EE | Sarvesh Bhardwaj,
Sarma B. K. Vrudhula,
David Blaauw:
Probability distribution of signal arrival times using Bayesian networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1784-1794 (2005) |
2004 |
3 | EE | Kaviraj Chopra,
Sarma B. K. Vrudhula,
Sarvesh Bhardwaj:
Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic.
VLSI Design 2004: 240- |
2003 |
2 | EE | Sarvesh Bhardwaj,
Sarma B. K. Vrudhula,
David Blaauw:
AU: Timing Analysis Under Uncertainty.
ICCAD 2003: 615-620 |
2002 |
1 | EE | Sarvesh Bhardwaj,
Sarma B. K. Vrudhula,
David Blaauw:
Estimation of signal arrival times in the presence of delay noise.
ICCAD 2002: 418-422 |