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Sarvesh Bhardwaj

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2008
21EEDeepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Temperature and Process Variations Aware Power Gating of Functional Units. VLSI Design 2008: 515-520
20EEDeepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma Vrudhul: Power Reduction of Functional Units Considering Temperature and Process Variations. VLSI Design 2008: 533-539
19EESarvesh Bhardwaj, Sarma B. K. Vrudhula, Amit Goel: A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1812-1825 (2008)
18EESarvesh Bhardwaj, Sarma B. K. Vrudhula: Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 445-455 (2008)
2007
17EEWenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu, Yu Cao: The Impact of NBTI on the Performance of Combinational and Sequential Circuits. DAC 2007: 364-369
16EEAmit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula: Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. PATMOS 2007: 125-137
15EESarvesh Bhardwaj, Sarma B. K. Vrudhula: A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations. VLSI Design 2007: 589-594
14EESarma B. K. Vrudhula, Sarvesh Bhardwaj: Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations. VLSI Design 2007: 9
2006
13EESarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula: Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. ASP-DAC 2006: 953-958
12EEPraveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda: Stochastic variational analysis of large power grids considering intra-die correlations. DAC 2006: 211-216
11EESarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao: Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. DAC 2006: 791-796
10EESarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula: A framework for statistical timing analysis using non-linear delay and slew models. ICCAD 2006: 225-230
9EESarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula: LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. ISQED 2006: 717-722
8EESarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula: Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. J. Low Power Electronics 2(2): 240-250 (2006)
2005
7EEVineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Meiling Wang: An efficient combinationality check technique for the synthesis of cyclic combinational circuits. ASP-DAC 2005: 212-215
6EESarvesh Bhardwaj, Sarma B. K. Vrudhula: Leakage minimization of nano-scale circuits in the presence of systematic and random variations. DAC 2005: 541-546
5 Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. ICCAD 2005: 713-718
4EESarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: Probability distribution of signal arrival times using Bayesian networks. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1784-1794 (2005)
2004
3EEKaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj: Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. VLSI Design 2004: 240-
2003
2EESarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: AU: Timing Analysis Under Uncertainty. ICCAD 2003: 615-620
2002
1EESarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: Estimation of signal arrival times in the presence of delay noise. ICCAD 2002: 418-422

Coauthor Index

1Vineet Agarwal [7]
2David Blaauw (David T. Blaauw) [1] [2] [4]
3Yu Cao [8] [9] [11] [13] [17]
4Kaviraj Chopra [3]
5Praveen Ghanta [10] [11] [12] [16]
6Amit Goel [16] [19]
7Navneeth Kankani [7]
8Deepa Kannan [20] [21]
9Frank Liu [17]
10Vipin Mohan [21]
11Rajendran Panda [12]
12Ravishankar Rao [7]
13Aviral Shrivastava [20] [21]
14Rakesh Vattikonda [17]
15Sarma Vrudhul [20]
16Sarma B. K. Vrudhula [1] [2] [3] [4] [5] [6] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [21]
17Janet Meiling Wang (Janet Meiling Wang Roveda) [7]
18Wenping Wang [17]
19Shengqi Yang [17]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)