Malay K. Ganai

2008
41	EE	Malay K. Ganai, Aarti Gupta: Tunneling and slicing: towards scalable BMC. DAC 2008: 137-142
40	EE	Sudipta Kundu, Malay K. Ganai, Rajesh Gupta: Partial order reduction for scalable testing of systemC TLM designs. DAC 2008: 936-941
39	EE	Malay K. Ganai, Aarti Gupta: Completeness in SMT-based BMC for Software Programs. DATE 2008: 831-836
38	EE	Malay K. Ganai, Weihong Li: d-TSR: Parallelizing SMT-Based BMC Using Tunnels over a Distributed Framework. Haifa Verification Conference 2008: 194-199
37	EE	Malay K. Ganai: Efficient Decision Procedure for Bounded Integer Non-linear Operations Using SMT(). Haifa Verification Conference 2008: 68-83
36	EE	Chao Wang, Malay K. Ganai, Chao Wang, Shuvendu K. Lahiri, Daniel Kroening: Embedded software verification: challenges and solutions. ICCAD 2008: 5
35	EE	Malay K. Ganai, Aarti Gupta: Efficient Modeling of Concurrent Systems in BMC. SPIN 2008: 114-133
34	EE	Aleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta, Pranav Ashar: Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1513-1517 (2008)
33	EE	Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Pranav Ashar: Efficient SAT-based bounded model checking for software verification. Theor. Comput. Sci. 404(3): 256-274 (2008)
2007
32	EE	Malay K. Ganai, Aarti Gupta: Efficient BMC for Multi-Clock Systems with Clocked Specifications. ASP-DAC 2007: 310-315
31	EE	Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazutoshi Wakabayashi: Synthesizing "Verification Aware" Models: Why and How? VLSI Design 2007: 50-56
30	EE	Malay K. Ganai, Aarti Gupta, Pranav Ashar: Verification of Embedded Memory Systems using Efficient Memory Modeling CoRR abs/0710.4666: (2007)
29	EE	Malay K. Ganai, Muralidhar Talupur, Aarti Gupta: SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in Solving Difference Logic. JSAT 3(1-2): 91-114 (2007)
2006
28	EE	Chao Wang, Aarti Gupta, Malay K. Ganai: Predicate learning and selective theory deduction for a difference logic solver. DAC 2006: 235-240
27	EE	Malay K. Ganai, Aarti Gupta: Accelerating high-level bounded model checking. ICCAD 2006: 794-801
26	EE	Aarti Gupta, Malay K. Ganai, Chao Wang: SAT-Based Verification Methods and Applications in Hardware Verification. SFM 2006: 108-143
25	EE	Malay K. Ganai, Muralidhar Talupur, Aarti Gupta: SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in a Separation Logic Solver. TACAS 2006: 135-150
24	EE	Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar: Efficient distributed SAT and SAT-based distributed Bounded Model Checking. STTT 8(4-5): 387-396 (2006)
2005
23	EE	Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Ilya Shlyakhter, Pranav Ashar: F-Soft: Software Verification Platform. CAV 2005: 301-306
22	EE	Malay K. Ganai, Aarti Gupta, Pranav Ashar: Beyond safety: customized SAT-based model checking. DAC 2005: 738-743
21	EE	Malay K. Ganai, Aarti Gupta, Pranav Ashar: Verification of Embedded Memory Systems using Efficient Memory Modeling. DATE 2005: 1096-1101
20	EE	Franjo Ivancic, Ilya Shlyakhter, Aarti Gupta, Malay K. Ganai: Model Checking C Programs Using F-SOFT. ICCD 2005: 297-308
19	EE	Chao Wang, Franjo Ivancic, Malay K. Ganai, Aarti Gupta: Deciding Separation Logic Formulae by SAT and Incremental Negative Cycle Elimination. LPAR 2005: 322-336
18	EE	Himanshu Jain, Franjo Ivancic, Aarti Gupta, Malay K. Ganai: Localization and Register Sharing for Predicate Abstraction. TACAS 2005: 397-412
17	EE	Malay K. Ganai, Aarti Gupta, Pranav Ashar: DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems. TACAS 2005: 575-580
16	EE	Aarti Gupta, Malay K. Ganai, Pranav Ashar: Lazy Constraints and SAT Heuristics for Proof-Based Abstraction. VLSI Design 2005: 183-188
2004
15	EE	Malay K. Ganai, Aarti Gupta, Pranav Ashar: Efficient Modeling of Embedded Memories in Bounded Model Checking. CAV 2004: 440-452
14	EE	Malay K. Ganai, Aarti Gupta, Pranav Ashar: Efficient SAT-based unbounded symbolic model checking using circuit cofactoring. ICCAD 2004: 510-517
13		Pranav Ashar, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Zijiang Yang: Efficient SAT-based Bounded Model Checking for Software Verification. ISoLA (Preliminary proceedings) 2004: 157-164
2003
12	EE	Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar: Abstraction and BDDs Complement SAT-Based BMC in DiVer. CAV 2003: 206-209
11	EE	Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar: Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking. CHARME 2003: 334-347
10	EE	Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar: Learning from BDDs in SAT-based bounded model checking. DAC 2003: 824-829
9	EE	Aarti Gupta, Malay K. Ganai, Zijiang Yang, Pranav Ashar: Iterative Abstraction using SAT-based BMC with Proof Analysis. ICCAD 2003: 416-423
2002
8	EE	Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik: Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. DAC 2002: 747-750
7	EE	Malay K. Ganai, Adnan Aziz: Improved SAT-Based Bounded Reachability Analysis. VLSI Design 2002: 729-734
6	EE	Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, Malay K. Ganai: Robust Boolean reasoning for equivalence checking and functional property verification. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1377-1394 (2002)
2001
5	EE	Malay K. Ganai, Adnan Aziz: Rarity based guided state space search. ACM Great Lakes Symposium on VLSI 2001: 97-102
4	EE	Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi: Circuit-based Boolean Reasoning. DAC 2001: 232-237
3	EE	Malay K. Ganai, Praveen Yalagandula, Adnan Aziz, Andreas Kuehlmann, Vigyan Singhal: SIVA: A System for Coverage-Directed State Space Search. J. Electronic Testing 17(1): 11-27 (2001)
1999
2	EE	Malay K. Ganai, Adnan Aziz, Andreas Kuehlmann: Enhancing Simulation with BDDs and ATPG. DAC 1999: 385-390
1		Tai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns: Performance Driven Synthesis for Pass-Transistor Logic. VLSI Design 1999: 372-377

Coauthor Index

1	Pranav Ashar	[8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [21] [22] [23] [24] [30] [33] [34]
2	Adnan Aziz	[1] [2] [3] [5] [7]
3	Jeffrey L. Burns	[1]
4	Srihari Cadambi	[34]
5	Aarti Gupta	[8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [39] [41]
6	Rajesh K. Gupta (Rajesh Gupta)	[40]
7	Franjo Ivancic	[13] [18] [19] [20] [23] [33] [34]
8	Himanshu Jain	[18]
9	Daniel Kroening (Daniel Kröning)	[36]
10	Florian Krohm	[6]
11	Andreas Kuehlmann	[2] [3] [4] [6]
12	Sudipta Kundu	[40]
13	Shuvendu K. Lahiri	[36]
14	Weihong Li	[38]
15	Tai-Hung Liu	[1]
16	Sharad Malik	[8]
17	Akira Mukaiyama	[31]
18	Viresh Paruthi	[4] [6]
19	Ilya Shlyakhter	[20] [23] [34]
20	Vigyan Singhal	[3]
21	Muralidhar Talupur	[25] [29]
22	Kazutoshi Wakabayashi	[31]
23	Chao Wang	[10] [12] [19] [26] [28] [36]
24	Praveen Yalagandula	[3]
25	Zijiang Yang	[9] [10] [11] [12] [13] [23] [24] [33] [34]
26	Aleksandr Zaks	[34]
27	Lintao Zhang	[8]

Colors in the list of coauthors