2009 | ||
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29 | EE | Tayfun Elmas, Shaz Qadeer, Serdar Tasiran: A calculus of atomic actions. POPL 2009: 2-15 |
2008 | ||
28 | EE | Alp Arslan Bayrakci, Alper Demir, Serdar Tasiran: Fast Monte Carlo Estimation of Timing Yield: Importance Sampling with Stochastic Logical Effort (ISLE) CoRR abs/0805.2627: (2008) |
27 | EE | Soner Yaldiz, Alper Demir, Serdar Tasiran: Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1264-1277 (2008) |
2007 | ||
26 | Oleg Sokolsky, Serdar Tasiran: Runtime Verification, 7th International Workshop, RV 2007, Vancover, Canada, March 13, 2007, Revised Selected Papers Springer 2007 | |
25 | EE | Tayfun Elmas, Shaz Qadeer, Serdar Tasiran: Goldilocks: a race and transaction-aware java runtime. PLDI 2007: 245-255 |
24 | EE | Serdar Tasiran, Tayfun Elmas: Rollback Atomicity. RV 2007: 188-201 |
2006 | ||
23 | EE | Tayfun Elmas, Shaz Qadeer, Serdar Tasiran: Goldilocks: Efficiently Computing the Happens-Before Relation Using Locksets. FATES/RV 2006: 193-208 |
22 | EE | M. Erkan Keremoglu, Serdar Tasiran, Tayfun Elmas: A classification of concurrency bugs in java benchmarks by developer intent. PADTAD 2006: 23-26 |
21 | EE | Tayfun Elmas, Serdar Tasiran: VyrdMC: Driving Runtime Refinement Checking with Model Checkers. Electr. Notes Theor. Comput. Sci. 144(4): 41-56 (2006) |
2005 | ||
20 | EE | Soner Yaldiz, Alper Demir, Serdar Tasiran, Paolo Ienne, Yusuf Leblebici: Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems. ESTImedia 2005: 135-140 |
19 | EE | Serdar Tasiran, Tayfun Elmas, Guven Bolukbasi, M. Erkan Keremoglu: A Novel Test Coverage Metric for Concurrently-Accessed Software Components. FATES 2005: 62-71 |
18 | EE | Tayfun Elmas, Serdar Tasiran, Shaz Qadeer: VYRD: verifYing concurrent programs by runtime refinement-violation detection. PLDI 2005: 27-37 |
17 | EE | Serdar Tasiran, Shaz Qadeer: Runtime Refinement Checking of Concurrent Data Structures. Electr. Notes Theor. Comput. Sci. 113: 163-179 (2005) |
2004 | ||
16 | EE | Serdar Tasiran, Yuan Yu, Brannon Batson: Linking Simulation with Formal Verification at a Higher Level. IEEE Design & Test of Computers 21(6): 472-482 (2004) |
2003 | ||
15 | EE | Serdar Tasiran, Yuan Yu, Brannon Batson: Using a formal specification and a model checker to monitor and direct simulation. DAC 2003: 356-361 |
14 | EE | Tamara Munzner, François Guimbretière, Serdar Tasiran, Li Zhang, Yunhong Zhou: TreeJuxtaposer: scalable tree comparison using Focus+Context with guaranteed visibility. ACM Trans. Graph. 22(3): 453-462 (2003) |
13 | EE | Rajeev Joshi, Leslie Lamport, John Matthews, Serdar Tasiran, Mark R. Tuttle, Yuan Yu: Checking Cache-Coherence Protocols with TLA+. Formal Methods in System Design 22(2): 125-131 (2003) |
2002 | ||
12 | EE | Shaz Qadeer, Serdar Tasiran: Promising Directions in Hardware Design Verification (invited). ISQED 2002: 381-387 |
11 | EE | Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani, Serdar Tasiran: An assume-guarantee rule for checking simulation. ACM Trans. Program. Lang. Syst. 24(1): 51-64 (2002) |
2001 | ||
10 | Serdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer: A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage. ICCD 2001: 82-88 | |
9 | EE | Serdar Tasiran, Kurt Keutzer: Coverage Metrics for Functional Validation of Hardware Designs. IEEE Design & Test of Computers 18(4): 36-45 (2001) |
1999 | ||
8 | EE | Ellen Sentovich, David L. Dill, Serdar Tasiran: Formal verification meets simulation (tutorial abstract). ICCAD 1999: 221 |
1998 | ||
7 | Rajeev Alur, Thomas A. Henzinger, Freddy Y. C. Mang, Shaz Qadeer, Sriram K. Rajamani, Serdar Tasiran: MOCHA: Modularity in Model Checking. CAV 1998: 521-525 | |
6 | EE | Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani, Serdar Tasiran: An Assume-Guarantee Rule for Checking Simulation. FMCAD 1998: 421-432 |
1997 | ||
5 | Serdar Tasiran, Robert K. Brayton: STARI: A Case Study in Compositional and Hierarchical Timing Verification. CAV 1997: 191-201 | |
1996 | ||
4 | Serdar Tasiran, Rajeev Alur, Robert P. Kurshan, Robert K. Brayton: Verifying Abstractions of Timed Systems. CONCUR 1996: 546-562 | |
1995 | ||
3 | Serdar Tasiran, Ramin Hojati, Robert K. Brayton: Language containment of non-deterministic omega-automata. CHARME 1995: 261-277 | |
1994 | ||
2 | EE | Adnan Aziz, Serdar Tasiran, Robert K. Brayton: BDD Variable Ordering for Interacting Finite State Machines. DAC 1994: 283-288 |
1 | EE | Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: HSIS: A BDD-Based Environment for Formal Verification. DAC 1994: 454-459 |