| 2008 |
|---|
| 7 | EE | Changzhong Chen,
Dharmendra Saraswat,
Ramachandra Achar,
Emad Gad,
Michel S. Nakhla,
Mustapha Chérif-Eddine Yagoub:
A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs With FD-PUL Parameters Using Integrated Congruence Transform.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 574-578 (2008) |
| 2007 |
|---|
| 6 | EE | Dharmendra Saraswat,
Ramachandra Achar,
Michel S. Nakhla:
Fast Passivity Verification and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels.
IEEE Trans. VLSI Syst. 15(1): 48-59 (2007) |
| 2006 |
|---|
| 5 | EE | Dharmendra Saraswat,
Ramachandra Achar,
Michel S. Nakhla:
Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering Parameters.
VLSI Design 2006: 667-671 |
| 2005 |
|---|
| 4 | EE | Dharmendra Saraswat,
Ramachandra Achar,
Michel S. Nakhla:
On passivity enforcement for macromodels of S-parameter based tabulated subnetworks.
ISCAS (4) 2005: 3777-3780 |
| 3 | EE | Dharmendra Saraswat,
Ramachandra Achar,
Michel S. Nakhla:
Projection Based Fast Passive Compact Macromodeling of High-Speed VLSI Circuits and Interconnects.
VLSI Design 2005: 629-633 |
| 2 | EE | Dharmendra Saraswat,
Ramachandra Achar,
Michel S. Nakhla:
Global Passivity Enforcement Algorithm for Macromodels of Interconnect Subnetworks Characterized by Tabulated Data.
IEEE Trans. VLSI Syst. 13(7): 819-832 (2005) |
| 2003 |
|---|
| 1 | EE | Dharmendra Saraswat,
Ramachandra Achar,
Michel S. Nakhla:
Passive macromodeling of subnetworks characterized by measured data.
ISCAS (3) 2003: 502-505 |
