| 2008 |
|---|
| 168 | EE | Yu Hu,
Xiang Fu,
Xiaoxin Fan,
Hideo Fujiwara:
Localized random access scan: Towards low area and routing overhead.
ASP-DAC 2008: 565-570 |
| 167 | EE | Tomokazu Yoneda,
Hideo Fujiwara:
Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects.
DATE 2008: 1366-1369 |
| 166 | EE | Dong Xiang,
Yang Zhao,
K. Chakrabarty,
Hideo Fujiwara:
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 999-1012 (2008) |
| 165 | EE | Hideo Fujiwara,
Hiroyuki Iwata,
Tomokazu Yoneda,
Chia Yee Ooi:
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1535-1544 (2008) |
| 164 | EE | Fawnizu Azmadi Hussin,
Tomokazu Yoneda,
Alex Orailoglu,
Hideo Fujiwara:
Scheduling Power-Constrained Tests through the SoC Functional Bus.
IEICE Transactions 91-D(3): 736-746 (2008) |
| 163 | EE | Tomokazu Yoneda,
Kimihiko Masuda,
Hideo Fujiwara:
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint.
IEICE Transactions 91-D(3): 747-755 (2008) |
| 162 | EE | Masato Nakasato,
Michiko Inoue,
Satoshi Ohtake,
Hideo Fujiwara:
Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors.
IEICE Transactions 91-D(3): 763-770 (2008) |
| 161 | EE | Thomas Edison Yu,
Tomokazu Yoneda,
Danella Zhao,
Hideo Fujiwara:
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints.
IEICE Transactions 91-D(3): 807-814 (2008) |
| 160 | EE | Fawnizu Azmadi Hussin,
Tomokazu Yoneda,
Hideo Fujiwara:
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time.
IEICE Transactions 91-D(7): 1999-2007 (2008) |
| 159 | EE | Fawnizu Azmadi Hussin,
Tomokazu Yoneda,
Hideo Fujiwara:
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints.
IEICE Transactions 91-D(7): 2008-2017 (2008) |
| 2007 |
|---|
| 158 | EE | Dan Zhao,
Unni Chandran,
Hideo Fujiwara:
Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores.
ASP-DAC 2007: 714-719 |
| 157 | EE | Fawnizu Azmadi Hussin,
Tomokazu Yoneda,
Alex Orailoglu,
Hideo Fujiwara:
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses.
ASP-DAC 2007: 720-725 |
| 156 | EE | Hiroyuki Iwata,
Tomokazu Yoneda,
Hideo Fujiwara:
A DFT Method for Time Expansion Model at Register Transfer Level.
DAC 2007: 682-687 |
| 155 | EE | Tomokazu Yoneda,
Masahiro Imanishi,
Hideo Fujiwara:
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers.
DATE 2007: 231-236 |
| 154 | EE | Fawnizu Azmadi Hussin,
Tomokazu Yoneda,
Hideo Fujiwara:
Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints.
European Test Symposium 2007: 35-42 |
| 153 | EE | Tsuyoshi Iwagaki,
Satoshi Ohtake,
Mineo Kaneko,
Hideo Fujiwara:
Efficient path delay test generation based on stuck-at test generation using checker circuitry.
ICCAD 2007: 418-423 |
| 152 | EE | Dan Zhao,
Ronghua Huang,
Tomokazu Yoneda,
Hideo Fujiwara:
Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing.
ISCAS 2007: 2942-2945 |
| 151 | EE | Thomas Edison Yu,
Tomokazu Yoneda,
Danella Zhao,
Hideo Fujiwara:
Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints.
VTS 2007: 369-374 |
| 150 | EE | Tomokazu Yoneda,
Akiko Shuto,
Hideyuki Ichihara,
Tomoo Inoue,
Hideo Fujiwara:
TAM Design and Optimization for Transparency-Based SoC Test.
VTS 2007: 381-388 |
| 149 | EE | Dong Xiang,
Mingjing Chen,
Hideo Fujiwara:
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST.
IEEE Trans. Computers 56(12): 1619-1628 (2007) |
| 148 | EE | Dong Xiang,
Kaiwei Li,
Jiaguang Sun,
Hideo Fujiwara:
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction.
IEEE Trans. Computers 56(4): 557-562 (2007) |
| 147 | EE | Yoshiyuki Nakamura,
Thomas Clouqueur,
Kewal K. Saluja,
Hideo Fujiwara:
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester.
IEEE Trans. VLSI Syst. 15(7): 790-800 (2007) |
| 146 | EE | Masato Nakasato,
Satoshi Ohtake,
Kewal K. Saluja,
Hideo Fujiwara:
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability.
IEICE Transactions 90-D(1): 296-305 (2007) |
| 145 | EE | Chia Yee Ooi,
Thomas Clouqueur,
Hideo Fujiwara:
Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tauk-Notation.
IEICE Transactions 90-D(8): 1202-1212 (2007) |
| 144 | EE | Ilia Polian,
Hideo Fujiwara:
Functional Constraints vs. Test Compression in Scan-Based Delay Testing.
J. Electronic Testing 23(5): 445-455 (2007) |
| 2006 |
|---|
| 143 | EE | Masahide Miyazaki,
Tomokazu Yoneda,
Hideo Fujiwara:
A memory grouping method for sharing memory BIST logic.
ASP-DAC 2006: 671-676 |
| 142 | EE | Ilia Polian,
Hideo Fujiwara:
Functional constraints vs. test compression in scan-based delay testing.
DATE 2006: 1039-1044 |
| 141 | EE | Tomokazu Yoneda,
Kimihiko Masuda,
Hideo Fujiwara:
Power-constrained test scheduling for multi-clock domain SoCs.
DATE 2006: 297-302 |
| 140 | EE | Mariane Comte,
Satoshi Ohtake,
Hideo Fujiwara,
Michel Renovell:
Electrical Behavior of GOS Fault affected Domino Logic Cell.
DELTA 2006: 183-189 |
| 139 | EE | Ilia Polian,
Bernd Becker,
Masato Nakasato,
Satoshi Ohtake,
Hideo Fujiwara:
Low-Cost Hardening of Image Processing Applications Against Soft Errors.
DFT 2006: 274-279 |
| 138 | EE | Chia Yee Ooi,
Hideo Fujiwara:
A New Class of Sequential Circuits with Acyclic Test Generation Complexity.
ICCD 2006 |
| 137 | EE | Dong Xiang,
Kaiwei Li,
Hideo Fujiwara,
Jiaguang Sun:
Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests.
ICCD 2006 |
| 136 | EE | Fawnizu Azmadi Hussin,
Tomokazu Yoneda,
Alex Orailoglu,
Hideo Fujiwara:
Power-Constrained SOC Test Schedules through Utilization of Functional Buses.
ICCD 2006 |
| 135 | EE | Tsuyoshi Iwagaki,
Satoshi Ohtake,
Hideo Fujiwara:
A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits.
VLSI-SoC 2006: 308-313 |
| 134 | EE | Yoshiyuki Nakamura,
Jacob Savir,
Hideo Fujiwara:
BIST Pretest of ICs: Risks and Benefits.
VTS 2006: 142-149 |
| 133 | EE | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Instruction-Based Self-Testing of Delay Faults in Pipelined Processors.
IEEE Trans. VLSI Syst. 14(11): 1203-1215 (2006) |
| 132 | EE | Erik Larsson,
Hideo Fujiwara:
System-on-chip test scheduling with reconfigurable core wrappers.
IEEE Trans. VLSI Syst. 14(3): 305-309 (2006) |
| 131 | EE | Yoshiyuki Nakamura,
Jacob Savir,
Hideo Fujiwara:
Effect of BIST Pretest on IC Defect Level.
IEICE Transactions 89-D(10): 2626-2636 (2006) |
| 130 | EE | Yoshiyuki Nakamura,
Thomas Clouqueur,
Kewal K. Saluja,
Hideo Fujiwara:
Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch.
IEICE Transactions 89-D(3): 1165-1172 (2006) |
| 129 | EE | Masahide Miyazaki,
Tomokazu Yoneda,
Hideo Fujiwara:
A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips.
IEICE Transactions 89-D(4): 1490-1497 (2006) |
| 128 | EE | Zhiqiang You,
Tsuyoshi Iwagaki,
Michiko Inoue,
Hideo Fujiwara:
A Low Power Deterministic Test Using Scan Chain Disable Technique.
IEICE Transactions 89-D(6): 1931-1939 (2006) |
| 127 | EE | Tomokazu Yoneda,
Hideo Fujiwara:
Design for consecutive transparency method of RTL circuits.
Systems and Computers in Japan 37(2): 1-10 (2006) |
| 2005 |
|---|
| 126 | EE | Dong Xiang,
Ming-Jing Chen,
Hideo Fujiwara:
Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST.
Asian Test Symposium 2005: 126-131 |
| 125 | EE | Tomokazu Yoneda,
Hisakazu Takakuwa,
Hideo Fujiwara:
Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability.
Asian Test Symposium 2005: 150-155 |
| 124 | EE | Yuki Yoshikaw,
Satoshi Ohtake,
Michiko Inoue,
Hideo Fujiwara:
Design for Testability Based on Single-Port-Change Delay Testing for Data Paths.
Asian Test Symposium 2005: 254-259 |
| 123 | EE | Thomas Clouqueur,
Hideo Fujiwara,
Kewal K. Saluja:
A Class of Linear Space Compactors for Enhanced Diagnostic.
Asian Test Symposium 2005: 260-265 |
| 122 | EE | Hideyuki Ichihara,
Tomoo Inoue,
Naoki Okamoto,
Toshinori Hosokawa,
Hideo Fujiwara:
An Effective Design for Hierarchical Test Generation Based on Strong Testability.
Asian Test Symposium 2005: 288-293 |
| 121 | EE | Hiroyuki Iwata,
Tomokazu Yoneda,
Satoshi Ohtake,
Hideo Fujiwara:
A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency.
Asian Test Symposium 2005: 306-311 |
| 120 | EE | Dong Xiang,
Kaiwei Li,
Hideo Fujiwara:
Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops.
Asian Test Symposium 2005: 318-323 |
| 119 | EE | Kazuko Kambe,
Michiko Inoue,
Hideo Fujiwara,
Tsuyoshi Iwagaki:
Efficient Constraint Extraction for Template-Based Processor Self-Test Generation.
Asian Test Symposium 2005: 444-449 |
| 118 | | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Testing Superscalar Processors in Functional Mode.
FPL 2005: 747-750 |
| 117 | EE | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Instruction-based delay fault self-testing of pipelined processor cores.
ISCAS (6) 2005: 5686-5689 |
| 116 | EE | Dong Xiang,
Ming-Jing Chen,
Jia-Guang Sun,
Hideo Fujiwara:
Improving test effectiveness of scan-based BIST by scan chain partitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 916-927 (2005) |
| 115 | EE | Chia Yee Ooi,
Thomas Clouqueur,
Hideo Fujiwara:
Classification of Sequential Circuits Based on tauk Notation and Its Applications.
IEICE Transactions 88-D(12): 2738-2747 (2005) |
| 114 | EE | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Delay Fault Testing of Processor Cores in Functional Mode.
IEICE Transactions 88-D(3): 610-618 (2005) |
| 113 | EE | Yoshiyuki Nakamura,
Jacob Savir,
Hideo Fujiwara:
Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST.
IEICE Transactions 88-D(6): 1210-1216 (2005) |
| 112 | EE | Zhiqiang You,
Ken-ichi Yamaguchi,
Michiko Inoue,
Jacob Savir,
Hideo Fujiwara:
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths.
IEICE Transactions 88-D(8): 1940-1947 (2005) |
| 2004 |
|---|
| 111 | EE | Kazuko Kambe,
Michiko Inoue,
Hideo Fujiwara:
Efficient Template Generation for Instruction-Based Self-Test of Processor Cores.
Asian Test Symposium 2004: 152-157 |
| 110 | EE | Zhiqiang You,
Ken-ichi Yamaguchi,
Michiko Inoue,
Jacob Savir,
Hideo Fujiwara:
Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths.
Asian Test Symposium 2004: 32-39 |
| 109 | EE | Debesh Kumar Das,
Tomoo Inoue,
Susanta Chakraborty,
Hideo Fujiwara:
Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity.
Asian Test Symposium 2004: 342-347 |
| 108 | EE | Chia Yee Ooi,
Hideo Fujiwara:
Classification of Sequential Circuits Based on ?k Notation.
Asian Test Symposium 2004: 348-353 |
| 107 | EE | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Instruction-Based Delay Fault Self-Testing of Processor Cores.
VLSI Design 2004: 933- |
| 106 | | Debesh K. Das,
Hideo Fujiwara,
Yungang Li,
Yinghua Min,
Shiyi Xu,
Yervant Zorian:
Design & Test Education in Asia.
IEEE Design & Test of Computers 21(4): 331-338 (2004) |
| 105 | EE | Erik Larsson,
Klas Arvidsson,
Hideo Fujiwara,
Zebo Peng:
Efficient test solutions for core-based designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 758-775 (2004) |
| 104 | EE | Debesh Kumar Das,
Satoshi Ohtake,
Hideo Fujiwara:
New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency.
J. Electronic Testing 20(3): 315-323 (2004) |
| 2003 |
|---|
| 103 | EE | Dong Xiang,
Ming-Jing Chen,
Jia-Guang Sun,
Hideo Fujiwara:
Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning.
Asian Test Symposium 2003: 12-17 |
| 102 | EE | Toshinori Hosokawa,
Hiroshi Date,
Masahide Miyazaki,
Michiaki Muraoka,
Hideo Fujiwara:
A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint.
Asian Test Symposium 2003: 130-135 |
| 101 | EE | Michiko Inoue,
Kazuhiro Suzuki,
Hiroyuki Okamoto,
Hideo Fujiwara:
Test Synthesis for Datapaths Using Datapath-Controller Functions.
Asian Test Symposium 2003: 294-299 |
| 100 | EE | Dong Xiang,
Shan Gu,
Hideo Fujiwara:
Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis.
Asian Test Symposium 2003: 300-305 |
| 99 | EE | Erik Larsson,
Hideo Fujiwara:
Optimal System-on-Chip Test Scheduling.
Asian Test Symposium 2003: 306-311 |
| 98 | EE | Masahide Miyazaki,
Toshinori Hosokawa,
Hiroshi Date,
Michiaki Muraoka,
Hideo Fujiwara:
A DFT Selection Method for Reducing Test Application Time of System-on-Chips.
Asian Test Symposium 2003: 412-417 |
| 97 | EE | Tsuyoshi Iwagaki,
Satoshi Ohtake,
Hideo Fujiwara:
Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models.
Asian Test Symposium 2003: 58-63 |
| 96 | EE | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Software-Based Delay Fault Testing of Processor Cores.
Asian Test Symposium 2003: 68-71 |
| 95 | EE | Satoshi Ohtake,
Kouhei Ohtani,
Hideo Fujiwara:
A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms.
DATE 2003: 10310-10315 |
| 94 | EE | Tomokazu Yoneda,
Tetsuo Uchiyama,
Hideo Fujiwara:
Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability.
ITC 2003: 415-422 |
| 93 | EE | Tomokazu Yoneda,
Hideo Fujiwara:
Design for Consecutive Transparency of Cores in System-on-a-Chip.
VTS 2003: 287-292 |
| 92 | EE | Erik Larsson,
Hideo Fujiwara:
Test Resource Partitioning and Optimization for SOC Designs.
VTS 2003: 319-324 |
| 91 | EE | Dong Xiang,
Yi Xu,
Hideo Fujiwara:
Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution.
IEEE Trans. Computers 52(8): 1063-1075 (2003) |
| 2002 |
|---|
| 90 | EE | Tomoo Inoue,
Tomokazu Miura,
Akio Tamura,
Hideo Fujiwara:
A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design.
Asian Test Symposium 2002: 128-133 |
| 89 | EE | Emil Gizdarski,
Hideo Fujiwara:
Fault Set Partition for Efficient Width Compression.
Asian Test Symposium 2002: 194-199 |
| 88 | EE | Erik Larsson,
Klas Arvidsson,
Hideo Fujiwara,
Zebo Peng:
Integrated Test Scheduling, Test Parallelization and TAMDesign.
Asian Test Symposium 2002: 397-404 |
| 87 | EE | Atlaf Ul Amin,
Satoshi Ohtake,
Hideo Fujiwara:
Design for Two-Pattern Testability of Controller-Data Path Circuits.
Asian Test Symposium 2002: 73-79 |
| 86 | EE | Dong Xiang,
Shan Gu,
Hideo Fujiwara:
Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis.
Asian Test Symposium 2002: 86- |
| 85 | EE | Michiko Inoue,
Chikateru Jinno,
Hideo Fujiwara:
An Extended Class of Sequential Circuits with Combinational Test Generation Complexity.
ICCD 2002: 200-205 |
| 84 | EE | Satoshi Ohtake,
Hideo Fujiwara,
Shunjiro Miwa:
A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits.
VTS 2002: 321-327 |
| 83 | EE | Emil Gizdarski,
Hideo Fujiwara:
SPIRIT: a highly robust combinational test generation algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1446-1458 (2002) |
| 82 | EE | Dong Xiang,
Hideo Fujiwara:
Handling the pin overhead problem of DFTs for high-quality and at-speed tests.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1105-1113 (2002) |
| 81 | EE | Michiko Inoue,
Emil Gizdarski,
Hideo Fujiwara:
Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption.
J. Electronic Testing 18(1): 55-62 (2002) |
| 80 | EE | Tomokazu Yoneda,
Hideo Fujiwara:
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores.
J. Electronic Testing 18(4-5): 487-501 (2002) |
| 79 | EE | Yoshiaki Katayama,
Eiichiro Ueda,
Hideo Fujiwara,
Toshimitsu Masuzawa:
A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings.
J. Parallel Distrib. Comput. 62(5): 865-884 (2002) |
| 78 | EE | Toshinori Hosokawa,
Tomoo Inoue,
Toshihiro Hiraoka,
Hideo Fujiwara:
Test sequence compaction methods for acyclic sequential circuits using a time expansion model.
Systems and Computers in Japan 33(10): 105-115 (2002) |
| 77 | EE | Takashi Ishimizu,
Akihiro Fujiwara,
Michiko Inoue,
Toshimitsu Masuzawa,
Hideo Fujiwara:
Parallel algorithms for selection on the BSP and BSP* models.
Systems and Computers in Japan 33(12): 97-107 (2002) |
| 76 | EE | Kunihiko Hayashi,
Michiko Inoue,
Toshimitsu Masuzawa,
Hideo Fujiwara:
A layout adjustment problem for disjoint rectangles preserving orthogonal order.
Systems and Computers in Japan 33(2): 31-42 (2002) |
| 75 | EE | Satoshi Ohtake,
Toshimitsu Masuzawa,
Hideo Fujiwara:
A nonscan DFT method for controllers to provide complete fault efficiency.
Systems and Computers in Japan 33(5): 64-75 (2002) |
| 2001 |
|---|
| 74 | EE | Satoshi Ohtake,
Shintaro Nagai,
Hiroki Wada,
Hideo Fujiwara:
A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability.
ASP-DAC 2001: 331-334 |
| 73 | EE | Md. Altaf-Ul-Amin,
Satoshi Ohtake,
Hideo Fujiwara:
Design for Hierarchical Two-Pattern Testability of Data Paths.
Asian Test Symposium 2001: 11-16 |
| 72 | EE | Tomokazu Yoneda,
Hideo Fujiwara:
A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability.
Asian Test Symposium 2001: 193-198 |
| 71 | EE | Ken-ichi Yamaguchi,
Hiroki Wada,
Toshimitsu Masuzawa,
Hideo Fujiwara:
BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths.
Asian Test Symposium 2001: 313-318 |
| 70 | EE | Emil Gizdarski,
Hideo Fujiwara:
A Framework for Low Complexity Static Learning.
DAC 2001: 546-549 |
| 69 | EE | Michiko Inoue,
Shinya Umetani,
Toshimitsu Masuzawa,
Hideo Fujiwara:
Adaptive Long-Lived O(k2)-Renaming with O(k2) Steps.
DISC 2001: 123-135 |
| 68 | EE | Debesh Kumar Das,
Bhargab B. Bhattacharya,
Satoshi Ohtake,
Hideo Fujiwara:
Testable Design of Sequential Circuits with Improved Fault Efficiency.
VLSI Design 2001: 128-133 |
| 67 | EE | Emil Gizdarski,
Hideo Fujiwara:
SPIRIT: A Highly Robust Combinational Test Generation Algorithm.
VTS 2001: 346-351 |
| 66 | EE | Chikara Ohori,
Michiko Inoue,
Toshimitsu Masuzawa,
Hideo Fujiwara:
A causal broadcast protocol for distributed mobile systems.
Systems and Computers in Japan 32(3): 65-75 (2001) |
| 2000 |
|---|
| 65 | EE | Satoshi Ohtake,
Hiroki Wada,
Toshimitsu Masuzawa,
Hideo Fujiwara:
A non-scan DFT method at register-transfer level to achieve complete fault efficiency.
ASP-DAC 2000: 599-604 |
| 64 | EE | Emil Gizdarski,
Hideo Fujiwara:
Spirit: satisfiability problem implementation for redundancy identification and test generation.
Asian Test Symposium 2000: 171-178 |
| 63 | EE | Toshimitsu Masuzawa,
Minoru Izutsu,
Hiroki Wada,
Hideo Fujiwara:
Single-control testability of RTL data paths for BIST.
Asian Test Symposium 2000: 210-215 |
| 62 | EE | Xiaowei Li,
Toshimitsu Masuzawa,
Hideo Fujiwara:
Strong self-testability for data paths high-level synthesis.
Asian Test Symposium 2000: 229-234 |
| 61 | EE | Michiko Inoue,
Emil Gizdarski,
Hideo Fujiwara:
A class of sequential circuits with combinational test generation complexity under single-fault assumption.
Asian Test Symposium 2000: 398-403 |
| 60 | | Tomoo Inoue,
Debesh Kumar Das,
Chiiho Sano,
Takahiro Mihara,
Hideo Fujiwara:
Test Generation for Acyclic Sequential Circuits with Hold Registers.
ICCAD 2000: 550-556 |
| 59 | | Dong Xiang,
Yi Xu,
Hideo Fujiwara:
Non-scan design for testability for synchronous sequential circuits based on conflict analysis.
ITC 2000: 520-529 |
| 58 | EE | Hideo Fujiwara:
A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity.
VLSI Design 2000: 288-293 |
| 57 | EE | Hiroki Wada,
Toshimitsu Masuzawa,
Kewal K. Saluja,
Hideo Fujiwara:
Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency.
VLSI Design 2000: 300-305 |
| 56 | EE | Hideo Fujiwara:
A New Class of Sequential Circuits with Combinational Test Generation Complexity.
IEEE Trans. Computers 49(9): 895-905 (2000) |
| 55 | EE | Xiaowei Li,
Paul Y. S. Cheung,
Hideo Fujiwara:
LFSR-Based Deterministic TPG for Two-Pattern Testing.
J. Electronic Testing 16(5): 419-426 (2000) |
| 54 | EE | Satoshi Ohtake,
Toshimitsu Masuzawa,
Hideo Fujiwara:
A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency.
J. Electronic Testing 16(5): 553-566 (2000) |
| 1999 |
|---|
| 53 | EE | Toshinori Hosokawa,
Toshihiro Hiraoka,
Tomoo Inoue,
Hideo Fujiwara:
Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model.
Asian Test Symposium 1999: 192- |
| 52 | EE | Debesh Kumar Das,
Satoshi Ohtake,
Hideo Fujiwara:
New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency.
Asian Test Symposium 1999: 263-268 |
| 51 | EE | Tomoya Takasaki,
Hideo Fujiwara,
Tomoo Inoue:
A High-Level Synthesis Approach to Partial Scan Design Based on Acyclic Structure.
Asian Test Symposium 1999: 309-314 |
| 50 | EE | Satoshi Ohtake,
Michiko Inoue,
Hideo Fujiwara:
A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description.
Asian Test Symposium 1999: 5-12 |
| 49 | EE | Takashi Ishimizu,
Akihiro Fujiwara,
Michiko Inoue,
Toshimitsu Masuzawa,
Hideo Fujiwara:
Parallel Algorithms for All Nearest Neighbors of Binary Images on the BSP Model.
ISPAN 1999: 394-399 |
| 48 | | Akihiro Fujiwara,
Michiko Inoue,
Toshimitsu Masuzawa,
Hideo Fujiwara:
A cost optimal parallel algorithm for weighted distance transforms.
Parallel Computing 25(4): 405-416 (1999) |
| 1998 |
|---|
| 47 | | Tomoya Takasaki,
Tomoo Inoue,
Hideo Fujiwara:
Partial Scan Design Methods Based on Internally Balanced Structure.
ASP-DAC 1998: 211-216 |
| 46 | EE | Tomoo Inoue,
Toshinori Hosokawa,
Takahiro Mihara,
Hideo Fujiwara:
An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits.
Asian Test Symposium 1998: 190-197 |
| 45 | EE | Satoshi Ohtake,
Toshimitsu Masuzawa,
Hideo Fujiwara:
A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency.
Asian Test Symposium 1998: 204-211 |
| 44 | EE | Michiko Inoue,
Takeshi Higashimura,
Kenji Noda,
Toshimitsu Masuzawa,
Hideo Fujiwara:
A High-Level Synthesis Method for Weakly Testable Data Paths.
Asian Test Symposium 1998: 40-45 |
| 43 | EE | Kunihiko Hayashi,
Michiko Inoue,
Toshimitsu Masuzawa,
Hideo Fujiwara:
A Layout Adjustment Problem for Disjoint Rectangles Preserving Orthogonal Order.
Graph Drawing 1998: 183-197 |
| 42 | | Sen Moriya,
Michiko Inoue,
Toshimitsu Masuzawa,
Hideo Fujiwara:
SelfStabilizing WaitFree Clock Synchronization with Bounded Space.
OPODIS 1998: 129-144 |
| 41 | EE | Tomoo Inoue,
Satoshi Miyazaki,
Hideo Fujiwara:
Universal Fault Diagnosis for Lookup Table FPGAs.
IEEE Design & Test of Computers 15(1): 39-44 (1998) |
| 40 | | Hideo Fujiwara:
Needed: Third-generation ATPG Benchmarks.
IEEE Design & Test of Computers 15(1): 96- (1998) |
| 39 | EE | Michiko Inoue,
Hideo Fujiwara:
An approach to test synthesis from higher level.
Integration 26(1-2): 101-116 (1998) |
| 38 | EE | Hiroshi Youra,
Tomoo Inoue,
Toshimitsu Masuzawa,
Hideo Fujiwara:
On the synthesis of synchronizable finite state machines with partial scan.
Systems and Computers in Japan 29(1): 53-62 (1998) |
| 37 | EE | Tomoya Takasaki,
Tomoo Inoue,
Hideo Fujiwara:
Partial scan design methods based on internally balanced structure.
Systems and Computers in Japan 29(10): 26-35 (1998) |
| 1997 |
|---|
| 36 | EE | Hiroyuki Michinishi,
Tokumi Yokohira,
Takuji Okamoto,
Tomoo Inoue,
Hideo Fujiwara:
Testing for the programming circuit of LUT-based FPGAs.
Asian Test Symposium 1997: 242-247 |
| 35 | EE | Tomoo Inoue,
Satoshi Miyazaki,
Hideo Fujiwara:
On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs.
Asian Test Symposium 1997: 276-281 |
| 34 | EE | Satoshi Ohtake,
Tomoo Inoue,
Hideo Fujiwara:
Sequential Test Generation Based on Circuit Pseudo-Transformation.
Asian Test Symposium 1997: 62-67 |
| 33 | EE | Akihiro Fujiwara,
Michiko Inoue,
Toshimitsu Masuzawa,
Hideo Fujiwara:
A Parallel Algorithm for Weighted Distance Transforms.
IPPS 1997: 407-412 |
| 32 | | Michiko Inoue,
Sen Moriya,
Toshimitsu Masuzawa,
Hideo Fujiwara:
Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System.
WDAG 1997: 290-304 |
| 31 | | Eiichiro Ueda,
Yoshiaki Katayama,
Toshimitsu Masuzawa,
Hideo Fujiwara:
A latency-optimal superstabilizing mutual exclusion protocol.
WSS 1997: 110-124 |
| 30 | EE | Akihiro Fujiwara,
Toshimitsu Masuzawa,
Hideo Fujiwara:
Parallel algorithms for connected-component problems of gray-scale images.
Systems and Computers in Japan 28(1): 74-86 (1997) |
| 29 | EE | Katsuyuki Takabatake,
Michiko Inoue,
Toshimitsu Masuzawa,
Hideo Fujiwara:
Non-scan design for testable data paths using thru operation.
Systems and Computers in Japan 28(10): 60-68 (1997) |
| 28 | EE | Hideo Fujiwara,
Satoshi Ohtake,
Tomoya Takasaki:
A sequential circuit structure with combinational test generation complexity and its application.
Systems and Computers in Japan 28(11): 11-21 (1997) |
| 27 | EE | Daisuke Yoshida,
Toshimitsu Masuzawa,
Hideo Fujiwara:
Fault-tolerant distributed algorithms for autonomous mobile robots with crash faults.
Systems and Computers in Japan 28(2): 33-43 (1997) |
| 1996 |
|---|
| 26 | EE | Tomoo Inoue,
Toshimitsu Masuzawa,
Hiroshi Youra,
Hideo Fujiwara:
An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan.
Asian Test Symposium 1996: 130-135 |
| 25 | EE | Hiroyuki Michinishi,
Tokumi Yokohira,
Takuji Okamoto,
Tomoo Inoue,
Hideo Fujiwara:
A Test Methodology for Interconnect Structures of LUT-based FPGAs.
Asian Test Symposium 1996: 68-74 |
| 24 | | Yasuro Sato,
Michiko Inoue,
Toshimitsu Masuzawa,
Hideo Fujiwara:
A Snapshot Algorithm for Distributed Mobile Systems.
ICDCS 1996: 734-743 |
| 1995 |
|---|
| 23 | EE | Tomoo Inoue,
Hideo Fujiwara,
Hiroyuki Michinishi,
Tokumi Yokohira,
Takuji Okamoto:
Universal test complexity of field-programmable gate arrays.
Asian Test Symposium 1995: 259-265 |
| 22 | EE | Tomoo Inoue,
Hironori Maeda,
Hideo Fujiwara:
A scheduling problem in test generation.
VTS 1995: 344-349 |
| 21 | EE | Hideo Fujiwara,
Tomoo Inoue:
Optimal Granularity and Scheme of Parallel Test Generation in a Distributed System.
IEEE Trans. Parallel Distrib. Syst. 6(7): 677-686 (1995) |
| 20 | EE | Akihiro Fujiwara,
Toshimitsu Masuzawa,
Hideo Fujiwara:
An Optimal Parallel Algorithm for the Euclidean Distance Maps of 2-D Binary Images.
Inf. Process. Lett. 54(5): 295-300 (1995) |
| 1993 |
|---|
| 19 | EE | Hideo Fujiwara,
Akihiro Yamamoto:
Parity-scan design to reduce the cost of test application.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1604-1611 (1993) |
| 1992 |
|---|
| 18 | | Takayuli Fujino,
Hideo Fujiwara:
An Efficient Test Generation Algorithm Based on Search State Dominance.
FTCS 1992: 246-253 |
| 17 | | Hideo Fujiwara,
Akihiro Yamamoto:
Parity-Scan Design to Reduce the Cost of Test Application.
ITC 1992: 283-292 |
| 1990 |
|---|
| 16 | | Hideo Fujiwara:
Computational Complexity of Controllability/Observability Problems for Combinational Circuits.
IEEE Trans. Computers 39(6): 762-767 (1990) |
| 15 | EE | Hideo Fujiwara,
Tomoo Inoue:
Optimal granularity of test generation in a distributed system.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(8): 885-892 (1990) |
| 1989 |
|---|
| 14 | EE | Hideo Fujiwara:
Enhancing random-pattern coverage of programmable logic arrays via masking technique.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(9): 1022-1025 (1989) |
| 1988 |
|---|
| 13 | | Hideo Fujiwara,
Osamu Fujisawa,
Kazunori Hikone:
Enhancing Random-Pattern Coverage of Programmable Logic Arrays via Masking Technique.
ITC 1988: 642-648 |
| 1987 |
|---|
| 12 | | Robert P. Treuer,
Vinod K. Agarwal,
Hideo Fujiwara:
A New Built-In Self-Test Design for PLA's with High Fault Coverage and Low Overhead.
IEEE Trans. Computers 36(3): 369-373 (1987) |
| 1985 |
|---|
| 11 | | Hideo Fujiwara,
Kewal K. Saluja,
Kozo Kinoshita:
A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead.
ITC 1985: 574-582 |
| 1984 |
|---|
| 10 | | Hideo Fujiwara:
A New PLA Design for Universal Testability.
IEEE Trans. Computers 33(8): 745-750 (1984) |
| 1983 |
|---|
| 9 | | Kewal K. Saluja,
Kozo Kinoshita,
Hideo Fujiwara:
An Easily Testable Design of Programmable Logic Arrays for Multiple Faults.
IEEE Trans. Computers 32(11): 1038-1046 (1983) |
| 8 | | Hideo Fujiwara,
Takeshi Shimono:
On the Acceleration of Test Generation Algorithms.
IEEE Trans. Computers 32(12): 1137-1144 (1983) |
| 1982 |
|---|
| 7 | | Hideo Fujiwara,
Shunichi Toida:
The Complexity of Fault Detection Problems for Combinational Logic Circuits.
IEEE Trans. Computers 31(6): 555-560 (1982) |
| 1981 |
|---|
| 6 | | Hideo Fujiwara,
Kozo Kinoshita:
A Design of Programmable Logic Arrays with Universal Tests.
IEEE Trans. Computers 30(11): 823-828 (1981) |
| 5 | | Hideo Fujiwara:
On Closedness and Test Complexity of Logic Circuits.
IEEE Trans. Computers 30(8): 556-562 (1981) |
| 1978 |
|---|
| 4 | | Hideo Fujiwara,
Kozo Kinoshita:
On the Computational Complexity of System Diagnosis.
IEEE Trans. Computers 27(10): 881-885 (1978) |
| 3 | | Hideo Fujiwara,
Kozo Kinoshita:
Connection Assignments for Probabilistically Diagnosable Systems.
IEEE Trans. Computers 27(3): 280-283 (1978) |
| 2 | | Hideo Fujiwara,
Kozo Kinoshita:
Some Existence Theorems for Probabilistically Diagnosable Systems.
IEEE Trans. Computers 27(4): 379-384 (1978) |
| 1975 |
|---|
| 1 | | Hideo Fujiwara,
Yoich Nagao,
Tsutomu Sasao,
Kozo Kinoshita:
Easily Testable Sequential Machines with Extra Inputs.
IEEE Trans. Computers 24(8): 821-826 (1975) |
