Pranav Ashar

2008
58	EE	Aleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta, Pranav Ashar: Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1513-1517 (2008)
57	EE	Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Pranav Ashar: Efficient SAT-based bounded model checking for software verification. Theor. Comput. Sci. 404(3): 256-274 (2008)
2007
56	EE	Malay K. Ganai, Aarti Gupta, Pranav Ashar: Verification of Embedded Memory Systems using Efficient Memory Modeling CoRR abs/0710.4666: (2007)
2006
55	EE	Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar: Efficient distributed SAT and SAT-based distributed Bounded Model Checking. STTT 8(4-5): 387-396 (2006)
2005
54	EE	Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Ilya Shlyakhter, Pranav Ashar: F-Soft: Software Verification Platform. CAV 2005: 301-306
53	EE	Malay K. Ganai, Aarti Gupta, Pranav Ashar: Beyond safety: customized SAT-based model checking. DAC 2005: 738-743
52	EE	Malay K. Ganai, Aarti Gupta, Pranav Ashar: Verification of Embedded Memory Systems using Efficient Memory Modeling. DATE 2005: 1096-1101
51	EE	Malay K. Ganai, Aarti Gupta, Pranav Ashar: DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems. TACAS 2005: 575-580
50	EE	Aarti Gupta, Malay K. Ganai, Pranav Ashar: Lazy Constraints and SAT Heuristics for Proof-Based Abstraction. VLSI Design 2005: 183-188
2004
49	EE	Malay K. Ganai, Aarti Gupta, Pranav Ashar: Efficient Modeling of Embedded Memories in Bounded Model Checking. CAV 2004: 440-452
48	EE	Malay K. Ganai, Aarti Gupta, Pranav Ashar: Efficient SAT-based unbounded symbolic model checking using circuit cofactoring. ICCAD 2004: 510-517
47		Pranav Ashar, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Zijiang Yang: Efficient SAT-based Bounded Model Checking for Software Verification. ISoLA (Preliminary proceedings) 2004: 157-164
2003
46	EE	Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar: Abstraction and BDDs Complement SAT-Based BMC in DiVer. CAV 2003: 206-209
45	EE	Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar: Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking. CHARME 2003: 334-347
44	EE	Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar: Learning from BDDs in SAT-based bounded model checking. DAC 2003: 824-829
43	EE	Aarti Gupta, Malay K. Ganai, Zijiang Yang, Pranav Ashar: Iterative Abstraction using SAT-based BMC with Proof Analysis. ICCAD 2003: 416-423
2002
42	EE	Srihari Cadambi, Chandra Mulpuri, Pranav Ashar: A fast, inexpensive and scalable hardware acceleration technique for functional simulation. DAC 2002: 570-575
41	EE	Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik: Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. DAC 2002: 747-750
40	EE	Aarti Gupta, Albert E. Casavant, Pranav Ashar, X. G. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi: Property-Specific Testbench Generation for Guided Simulation. VLSI Design 2002: 524-
39	EE	Farzan Fallah, Pranav Ashar, Srinivas Devadas: Functional vector generation for sequential HDL models under an observability-based code coverage metric. IEEE Trans. VLSI Syst. 10(6): 919-923 (2002)
2001
38	EE	Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav Ashar: Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation. DAC 2001: 536-541
37	EE	Albert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar: Property-specific witness graph generation for guided simulation. DATE 2001: 799
36	EE	Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik: Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs. ICCAD 2001: 286-292
35	EE	Pranav Ashar, Aarti Gupta, Sharad Malik: Using complete-1-distinguishability for FSM equivalence checking. ACM Trans. Design Autom. Electr. Syst. 6(4): 569-590 (2001)
2000
34	EE	Aarti Gupta, Zijiang Yang, Pranav Ashar, Anubhav Gupta: SAT-Based Image Computation with Application in Reachability Analysis. FMCAD 2000: 354-371
33	EE	Aarti Gupta, Pranav Ashar: Fast Error Diagnosis for Combinational Verification. VLSI Design 2000: 442-448
32	EE	Yang Xia, Pranav Ashar: Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture. VLSI Design 2000: 449-
1999
31	EE	Aarti Gupta, Pranav Ashar, Sharad Malik: Exploiting Retiming in a Guided Simulation Based Validation Methodology. CHARME 1999: 350-353
30	EE	Farzan Fallah, Pranav Ashar, Srinivas Devadas: Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage. DAC 1999: 666-671
29	EE	Zhen Luo, Margaret Martonosi, Pranav Ashar: An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking. FCCM 1999: 158-167
28	EE	Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya: Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. ICCD 1999: 458-466
27	EE	Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik: Using configurable computing to accelerate Boolean satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 861-868 (1999)
1998
26	EE	Peixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi: Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability. DAC 1998: 194-199
25	EE	Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik: Accelerating Boolean Satisfiability with Configurable Hardware. FCCM 1998: 186-195
24	EE	Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik: Solving Boolean Satisfiability with Dynamic Hardware Configurations. FPL 1998: 326-335
23	EE	Pranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama: Verification of RTL generated from scheduled behavior in a high-level synthesis flow. ICCAD 1998: 517-524
22	EE	Aarti Gupta, Pranav Ashar: Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking. VLSI Design 1998: 222-225
21	EE	Vivek Tiwari, Sharad Malik, Pranav Ashar: Guarded evaluation: pushing power management to logic synthesis/design. IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 1051-1060 (1998)
1997
20	EE	Aarti Gupta, Sharad Malik, Pranav Ashar: Toward Formalizing a Validation Methodology Using Simulation Coverage. DAC 1997: 740-745
1996
19	EE	José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar: Scheduling Techniques to Enable Power Management. DAC 1996: 349-352
18	EE	Pranav Ashar, Aarti Gupta, Sharad Malik: Using complete-1-distinguishability for FSM equivalence checking. ICCAD 1996: 346-353
1995
17	EE	Pranav Ashar, Sharad Malik: Fast functional simulation using branching programs. ICCAD 1995: 408-412
16	EE	Vivek Tiwari, Sharad Malik, Pranav Ashar: Guarded evaluation: pushing power management to logic synthesis/design. ISLPD 1995: 221-226
15	EE	Anand Raghunathan, Pranav Ashar, Sharad Malik: Test generation for cyclic combinational circuits. VLSI Design 1995: 104-109
14	EE	Anand Raghunathan, Pranav Ashar, Sharad Malik: Test generation for cyclic combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(11): 1408-1414 (1995)
13	EE	Pranav Ashar, Sharad Malik: Functional timing analysis using ATPG. IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 1025-1030 (1995)
12	EE	Pranav Ashar, Sujit Dey, Sharad Malik: Exploiting multicycle false paths in the performance optimization of sequential logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1067-1075 (1995)
1994
11	EE	Pranav Ashar, Sharad Malik: Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications. DAC 1994: 77-80
10	EE	Pranav Ashar, Matthew Cheong: Efficient breadth-first manipulation of binary decision diagrams. ICCAD 1994: 622-627
1993
9	EE	Vivek Tiwari, Pranav Ashar, Sharad Malik: Technology Mapping for Lower Power. DAC 1993: 74-79
8		Pranav Ashar, Srinivas Devadas, Kurt Keutzer: Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. Formal Methods in System Design 2(1): 93-112 (1993)
1992
7	EE	Pranav Ashar, Sujit Dey, Sharad Malik: Exploiting multi-cycle false paths in the performance optimization of sequential circuits. ICCAD 1992: 510-517
1991
6		Pranav Ashar, Abhijit Ghosh, Srinivas Devadas: Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams. ICCD 1991: 259-264
5		Pranav Ashar, Srinivas Devadas, Kurt Keutzer: Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. ITC 1991: 887-896
4	EE	Pranav Ashar, Srinivas Devadas, A. Richard Newton: Optimum and heuristic algorithms for an approach to finite state machine decomposition. IEEE Trans. on CAD of Integrated Circuits and Systems 10(3): 296-310 (1991)
3	EE	Pranav Ashar, Srinivas Devadas, A. Richard Newton: Irredundant interacting sequential machines via optimal logic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 10(3): 311-325 (1991)
1990
2	EE	Pranav Ashar, Srinivas Devadas, A. Richard Newton: A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines. DAC 1990: 601-606
1		Pranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton: Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. ICCAD 1990: 84-87

Coauthor Index

1	Subhrajit Bhattacharya	[23] [28]
2	Srihari Cadambi	[42] [58]
3	Albert E. Casavant	[37] [40]
4	Matthew Cheong	[10]
5	Srinivas Devadas	[1] [2] [3] [4] [5] [6] [8] [19] [30] [39]
6	Sujit Dey	[7] [12]
7	Farzan Fallah	[30] [39]
8	Malay K. Ganai	[41] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58]
9	Abhijit Ghosh	[1] [6]
10	Aarti Gupta	[18] [20] [22] [28] [31] [33] [34] [35] [36] [37] [38] [40] [41] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58]
11	Anubhav Gupta	[34] [38]
12	Franjo Ivancic	[47] [54] [57] [58]
13	Kurt Keutzer	[5] [8]
14	S. Liu	[37]
15	X. G. Liu	[40]
16	Zhen Luo	[29]
17	Sharad Malik	[7] [9] [11] [12] [13] [14] [15] [16] [17] [18] [20] [21] [24] [25] [26] [27] [31] [35] [36] [41]
18	Margaret Martonosi	[24] [25] [26] [27] [29]
19	Ashutosh Mauskar	[19]
20	José C. Monteiro (José Monteiro)	[19]
21	Akira Mukaiyama	[23] [37] [40]
22	Chandra Mulpuri	[42]
23	A. Richard Newton	[1] [2] [3] [4]
24	Anand Raghunathan	[14] [15] [23] [28]
25	Ilya Shlyakhter	[54] [58]
26	Vivek Tiwari	[9] [16] [21]
27	Kazutoshi Wakabayashi	[37] [40]
28	Chao Wang	[44] [46]
29	Yang Xia	[32]
30	Zijiang Yang	[34] [36] [38] [43] [44] [45] [46] [47] [54] [55] [57] [58]
31	Aleksandr Zaks	[58]
32	Lintao Zhang	[36] [41]
33	Peixin Zhong	[24] [25] [26] [27]

Colors in the list of coauthors