| 2009 |
|---|
| 42 | EE | Jwu-E Chen,
Pei-Wen Luo,
Chin-Long Wey:
Yield evaluation of analog placement with arbitrary capacitor ratio.
ISQED 2009: 179-184 |
| 2008 |
|---|
| 41 | EE | Chun-Ming Huang,
Chien-Ming Wu,
Chih-Chyau Yang,
Chin-Long Wey:
PrSoC: Programmable System-on-chip (SoC) for silicon prototyping.
ISCAS 2008: 3382-3385 |
| 40 | EE | Pei-Wen Luo,
Jwu-E Chen,
Chin-Long Wey,
Liang-Chia Cheng,
Ji-Jan Chen,
Wen-Ching Wu:
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2097-2101 (2008) |
| 2007 |
|---|
| 39 | EE | Chin-Long Wey,
Wei-Chien Tang,
Shin-Yo Lin:
Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications.
ISVLSI 2007: 98-106 |
| 38 | EE | Jin-Fu Li,
Tsu-Wei Tseng,
Chin-Long Wey:
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories
CoRR abs/0710.4747: (2007) |
| 2006 |
|---|
| 37 | EE | Tsung-Han Tsai,
Yung-Tsung Wang,
Jui Hong Hung,
Chin-Long Wey:
Compressed domain content-based retrieval of MP3 audio example using quantization tree indexing and melody-line tracking method.
ISCAS 2006 |
| 2005 |
|---|
| 36 | EE | Shaolei Quan,
Qiang Qiang,
Chin-Long Wey:
Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test.
Asian Test Symposium 2005: 70-75 |
| 35 | EE | Jin-Fu Li,
Tsu-Wei Tseng,
Chin-Long Wey:
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories.
DATE 2005: 574-579 |
| 34 | EE | Shaolei Quan,
Meng-Yao Liu,
Chin-Long Wey:
Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress.
DFT 2005: 563-572 |
| 33 | EE | Shaolei Quan,
Qiang Qiang,
Chin-Long Wey:
A novel reconfigurable architecture of low-power unsigned multiplier for digital signal processing.
ISCAS (4) 2005: 3327-3330 |
| 2004 |
|---|
| 32 | EE | Shaolei Quan,
Chin-Long Wey:
A noise optimization technique for codesign of CMOS radio-frequency low noise amplifiers and low-quality spiral inductors.
ACM Great Lakes Symposium on VLSI 2004: 178-182 |
| 31 | EE | Chin-Long Wey,
Mohammad Athar Khalil,
Jim Liu,
Gregory Wierzba:
Hierarchical extreme-voltage stress test of analog CMOS ICs for gate-oxide reliability enhancement.
ACM Great Lakes Symposium on VLSI 2004: 322-327 |
| 30 | EE | Chin-Long Wey,
Meng-Yao Liu:
Burn-In Stress Test of Analog CMOS ICs.
Asian Test Symposium 2004: 360-365 |
| 2001 |
|---|
| 29 | | Mohammad Athar Khalil,
Chin-Long Wey:
Extreme-voltage stress vector generation of analog CMOS ICs for gate-oxide reliability enhancement.
ITC 2001: 348-357 |
| 28 | EE | Mohammad Athar Khalil,
Chin-Long Wey:
High-Voltage Stress Test Paradigms of Analog CMOS ICs for Gate-Oxide Reliability Enhancement.
VTS 2001: 333-338 |
| 2000 |
|---|
| 27 | EE | Chin-Long Wey,
Adam Osseiran,
José Luis Huertas,
Yeon-Chen Nieu:
Mixed-Signal SoC Testing: Is Mixed-Signal Design-for-Test on Its Way.
Asian Test Symposium 2000: 15- |
| 1998 |
|---|
| 26 | EE | Manuel Jiménez,
Chin-Long Wey,
Michael A. Shanblatt:
Mapping Multiplication Algorithms into a Family of LUT-based FPGAs (Abstract).
FPGA 1998: 259 |
| 25 | | Chin-Long Wey,
Ming-Der Shieh:
Design of a High-Speed Square Generator.
IEEE Trans. Computers 47(9): 1021-1026 (1998) |
| 1997 |
|---|
| 24 | | Cheng-Ping Wang,
Chin-Long Wey:
Development of Hierarchical Testability Design Methodologies for Analog/Mixed-Signal Integrated Circuits.
ICCD 1997: 468-473 |
| 1996 |
|---|
| 23 | EE | Cheng-Ping Wang,
Chin-Long Wey:
Test Generation Of Analog Switched-Current Circuits.
Asian Test Symposium 1996: 276-281 |
| 22 | | Chin-Long Wey:
On Design of Efficient Square Generator.
ICCD 1996: 506- |
| 21 | EE | Chin-Long Wey:
Built-in self-test (BIST) design of high-speed carry-free dividers.
IEEE Trans. VLSI Syst. 4(1): 141-145 (1996) |
| 1995 |
|---|
| 20 | EE | Chin-Long Wey,
Haiyan Wang,
Cheng-Ping Wang:
A self-timed redundant-binary number to binary number converter for digital arithmetic processors.
ICCD 1995: 386- |
| 19 | EE | Tzu-Hsi Pan,
Hyon-Sok Kay,
Youngsun Chun,
Chin-Long Wey:
High-radix SRT division with speculation of quotient digits .
ICCD 1995: 479- |
| 18 | | Chin-Long Wey:
Built-In Self Test (BIST) Design of High-Speed Carry-Free Dividers.
ISCAS 1995: 1916-1919 |
| 17 | | Jun-Woo Kang,
Chin-Long Wey,
P. David Fisher:
Application of Bipartite Graphs for Achieving Race-Free State Assignment.
IEEE Trans. Computers 44(8): 1002-1011 (1995) |
| 16 | EE | Chin-Long Wey,
Shoba Krishnan,
Sondes Sahli:
Test generation and concurrent error detection in current-mode A/D converters.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(10): 1291-1298 (1995) |
| 1994 |
|---|
| 15 | | Chin-Long Wey:
Concurrent Error Detection in High Speed Carry-free Division Using Alternative Input Data.
ICCD 1994: 124-127 |
| 1993 |
|---|
| 14 | | Chin-Long Wey,
Ming-Der Shieh,
P. David Fisher:
ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits.
ICCD 1993: 159-162 |
| 13 | | Jun-Woo Kang,
Chin-Long Wey,
P. David Fisher:
Race-free state assignments using bipartite graphs.
ISCAS 1993: 2560-2563 |
| 1992 |
|---|
| 12 | | Shoba Krishnan,
Sondes Sahli,
Chin-Long Wey:
Test Generation and Concurrent Error Detection in Current-Mode A/D Converters.
ITC 1992: 312-320 |
| 1991 |
|---|
| 11 | | Chin-Long Wey:
Concurrent Error Detection in Array Dividers by Alternating Input Data.
ICCD 1991: 114-117 |
| 1990 |
|---|
| 10 | EE | Chin-Long Wey,
Jyhyeung Ding,
Tsin-Yuan Chang:
Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement.
DAC 1990: 327-332 |
| 9 | EE | Chin-Long Wey,
Tsin-Yuan Chang:
An efficient output phase assignment for PLA minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(1): 1-7 (1990) |
| 1989 |
|---|
| 8 | | Chin-Long Wey:
Fault Location in Repairable Programmable Logic Arrays.
ITC 1989: 679-685 |
| 1988 |
|---|
| 7 | EE | Chin-Long Wey,
Tsin-Yuan Chang:
PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs.
DAC 1988: 421-426 |
| 6 | EE | Shek-Wayne Chan,
Chin-Long Wey:
The design of concurrent error diagnosable systolic arrays for band matrix multiplications.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(1): 21-37 (1988) |
| 5 | EE | Chin-Long Wey:
On yield consideration for the design of redundant programmable logic arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(4): 528-535 (1988) |
| 1987 |
|---|
| 4 | EE | Chin-Long Wey:
On Yield Consideration for the Design of Redundant Programmable Logic Arrays.
DAC 1987: 622-628 |
| 3 | | Chin-Long Wey,
Fabrizio Lombardi:
On a Novel Self-Test Approach to Digital Testing.
Comput. J. 30(3): 258-267 (1987) |
| 2 | EE | Chin-Long Wey,
Fabrizio Lombardi:
On the Repair of Redundant RAM's.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(2): 222-231 (1987) |
| 1985 |
|---|
| 1 | | Fabrizio Lombardi,
Chin-Long Wey:
On a Multiprocessor System with Dynamic Redundancy.
IEEE Real-Time Systems Symposium 1985: 3-12 |
