Sotirios G. Ziavras

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58EEShuai Wang, Jie Hu, Sotirios G. Ziavras: BTB Access Filtering: A Low Energy and High Performance Design. ISVLSI 2008: 81-86
57EEShuai Wang, Jie Hu, Sotirios G. Ziavras: Self-Adaptive Data Caches for Soft-Error Reliability. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1503-1507 (2008)
56EEShuai Wang, Hongyan Yang, Jie Hu, Sotirios G. Ziavras: Asymmetrically banked value-aware register files for low-energy and high-performance. Microprocessors and Microsystems - Embedded Hardware Design 32(3): 171-182 (2008)
55EEDejiang Jin, Sotirios G. Ziavras: Robust scalability analysis and SPM case studies. The Journal of Supercomputing 43(3): 199-223 (2008)
54 Xiaofang Wang, Sotirios G. Ziavras, Jie Hu: Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors. ERSA 2007: 61-70
53EEKanchan Devarakonda, Sotirios G. Ziavras, Roberto Rojas-Cessa: Measuring Network Parameters with Hardware Support. ICNS 2007: 2
52EEDejiang Jin, Sotirios G. Ziavras: A Study of Data Exchange Protocols for the Grid Computing Environment. ICNS 2007: 75
51EEXiaofang Wang, Sotirios G. Ziavras: Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors. ISQED 2007: 386-391
50EEShuai Wang, Hongyan Yang, Jie Hu, Sotirios G. Ziavras: Asymmetrically Banked Value-Aware Register Files. ISVLSI 2007: 363-368
49EEHongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie Hu: Vector Processing Support for FPGA-Oriented High Performance Applications. ISVLSI 2007: 447-448
48EEMuhammad Z. Hasan, Sotirios G. Ziavras: Runtime Partial Reconfiguration for Embedded Vector Processors. ITNG 2007: 983-988
47EEHongyan Yang, Sotirios G. Ziavras, Jie Hu: FPGA-based Vector Processing for Matrix Operations. ITNG 2007: 989-994
46EESotirios G. Ziavras, Alexandros V. Gerbessiotis, Rohan Bafna: Coprocessor design to support MPI primitives in configurable multiprocessors. Integration 40(3): 235-252 (2007)
45EEMuhammad Z. Hasan, Sotirios G. Ziavras: Partially Reconfigurable Vector Processor for Embedded Applications. JCP 2(9): 60-66 (2007)
44EEJie Hu, Shuai Wang, Sotirios G. Ziavras: In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability. DSN 2006: 281-290
43EEXiaofang Wang, Sotirios G. Ziavras: System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors. ICCD 2006
42EEShuai Wang, Jie Hu, Sotirios G. Ziavras: On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors. ICSAMOS 2006: 14-20
41EEXizhen Xu, Sotirios G. Ziavras: A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers. IEICE Transactions 89-D(2): 639-646 (2006)
40EEJie Hu, Greg M. Link, Johnsy K. John, Shuai Wang, Sotirios G. Ziavras: Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. Asia-Pacific Computer Systems Architecture Conference 2005: 200-214
39EEXizhen Xu, Sotirios G. Ziavras, Tae-Gyu Chang: An FPGA-Based Parallel Accelerator for Matrix Multiplications in the Newton-Raphson Method. EUC 2005: 458-468
38EEMuhammad Z. Hasan, Sotirios G. Ziavras: FPGA-Based Vector Processing for Solving Sparse Sets of Equations. FCCM 2005: 331-332
37 Xiaofang Wang, Sotirios G. Ziavras: A Framework for Dynamic Resource Assignment and Scheduling on Reconfigurable Mixed-Mode On-Chip Multiprocessors. FPT 2005: 51-58
36EEJohnsy K. John, Jie S. Hu, Sotirios G. Ziavras: Optimizing the Thermal Behavior of Subarrayed Data Caches. ICCD 2005: 625-630
35EEXizhen Xu, Sotirios G. Ziavras: H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication. ICCD 2005: 671-676
34EEDejiang Jin, Sotirios G. Ziavras: Modeling distributed data representation and its effect on parallel data accesses. J. Parallel Distrib. Comput. 65(10): 1281-1289 (2005)
33EEXiaofang Wang, Sotirios G. Ziavras: A Configurable Multiprocessor and Dynamic Load Balancing for Parallel LU Factorization. IPDPS 2004
32EEXiaofang Wang, Sotirios G. Ziavras: Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines. Concurrency and Computation: Practice and Experience 16(4): 319-343 (2004)
31EEDejiang Jin, Sotirios G. Ziavras: A Super-Programming Approach for Mining Association Rules in Parallel on PC Clusters. IEEE Trans. Parallel Distrib. Syst. 15(9): 783-794 (2004)
30EESatchidanand G. Haridas, Sotirios G. Ziavras: FPGA implementation of a Cholesky algorithm for a shared-memory multiprocessor architecture. Parallel Algorithms Appl. 19(4): 211-226 (2004)
29 Xizhen Xu, Sotirios G. Ziavras: Iterative Methods for Solving Linear Systems of Equations on FPGA-Based Machines. Computers and Their Applications 2003: 472-475
28EEDejiang Jin, Sotirios G. Ziavras: Load Balancing on PC Clusters with the Super-Programming Model. ICPP Workshops 2003: 63-70
27EEXiaofang Wang, Sotirios G. Ziavras: Parallel Direct Solution of Linear Equations on FPGA-Based Machines. IPDPS 2003: 113
26EESotirios G. Ziavras, Qian Wang, Paraskevi Papathanasiou: Viable Architectures for High-Performance Computing. Comput. J. 46(1): 36-54 (2003)
25EESotirios G. Ziavras: Processor design based on dataflow concurrency. Microprocessors and Microsystems 27(4): 199-220 (2003)
24EESegreen Ingersoll, Sotirios G. Ziavras: Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs). Microprocessors and Microsystems 26(6): 263-280 (2002)
23EESotirios G. Ziavras: Versatile Processor Design for Efficiency and High Performance. ISPAN 2000: 266-273
22EESotirios G. Ziavras, Haim Grebel, Anthony T. Chronopoulos, Florent Marcelli: A new-generation parallel computer and its performance evaluation. Future Generation Comp. Syst. 17(3): 315-333 (2000)
21 Qian Wang, Sotirios G. Ziavras: Network Embedding Techniques for a New Class of Feasible Parallel Architectures. Applied Informatics 1999: 566-568
20EEQian Wang, Sotirios G. Ziavras: Powerful and Feasible Processor Interconnections With an Evaluation of Their Communications Capabilities. ISPAN 1999: 222-229
19 Sotirios G. Ziavras, Sanjay Krishnamurthy: Evaluating the communications capabilities of the generalized hypercube interconnection network. Concurrency - Practice and Experience 11(6): 281-300 (1999)
18 Xi Li, Sotirios G. Ziavras, Constantine N. Manikopoulos: Parallel generation of adaptive multiresolution structures for image processing. Concurrency - Practice and Experience 9(4): 241-254 (1997)
17EESotirios G. Ziavras: Performance Analysis for an Important Class of Parallel-Processing Networks. ISPAN 1996: 500-506
16 Xi Li, Sotirios G. Ziavras, Constantine N. Manikopoulos: Parallel DSP algorithms on TurboNet: an experimental system with hybrid message-passing/shared-memory architecture. Concurrency - Practice and Experience 8(5): 387-411 (1996)
15 Sotirios G. Ziavras, Arup Mukherjee: Data Broadcasting and Reduction, Prefix Computation, and Sorting on Reduces Hypercube Parallel Computer. Parallel Computing 22(4): 595-606 (1996)
14 Sotirios G. Ziavras, Michalis A. Sideras: Facilitating High-Performance Image Analysis on Reduced Hypercube (RH) Parallel Computers. IJPRAI 9(4): 679-698 (1995)
13 Sotirios G. Ziavras: Scalable Multifolded Hypercubes for versatile Parallel Computers. Parallel Processing Letters 5: 241-250 (1995)
12EESotirios G. Ziavras, Devenkumar P. Shah: High-performance emulation of hierarchical structures on hypercube supercomputers. Concurrency - Practice and Experience 6(2): 85-100 (1994)
11EESotirios G. Ziavras: RH: A Versatile Family of Reduced Hypercube Interconnection Networks. IEEE Trans. Parallel Distrib. Syst. 5(11): 1210-1220 (1994)
10 Sotirios G. Ziavras, Peter Meer: Adaptive Multiresolution Structures for Image Processing on Parallel Computers. J. Parallel Distrib. Comput. 23(3): 475-483 (1994)
9EESotirios G. Ziavras, Muhammad A. Siddiqui: Pyramid mappings onto hypercubes for computer vision: Connection machine comparative study. Concurrency - Practice and Experience 5(6): 471-489 (1993)
8EESotirios G. Ziavras: Efficient Mapping Algorithms for a Class of Hierarchical Systems. IEEE Trans. Parallel Distrib. Syst. 4(11): 1230-1245 (1993)
7EESotirios G. Ziavras: Connected component labelling on the BLITZEN massively parallel processor. Image Vision Comput. 11(10): 665-668 (1993)
6 Sotirios G. Ziavras: Connection Machine Results for Pyramid Embedding Algorithms. CONPAR 1992: 31-36
5 Nagasimha G. Haravu, Sotirios G. Ziavras: Processor Allocation for a Class of Hypercube-Like Supercomputers. SC 1992: 740-749
4 Sotirios G. Ziavras: On the Problem of Expanding Hypercube-Based Systems. J. Parallel Distrib. Comput. 16(1): 41-53 (1992)
3 Sotirios G. Ziavras: Techniques for Mapping Deterministic Algorithms onto Multi-Level Systems. ICPP (1) 1990: 226-233
2EESotirios G. Ziavras, Nikitas A. Alexandridis: Improved algorithms for translation of pictures represented by leaf codes. Image Vision Comput. 6(1): 13-20 (1988)
1 Nikitas A. Alexandridis, Sotirios G. Ziavras, P. D. Tsanakas: Architectural Adaptations for Hierarchical Image Processing/Transmission. ICC 1986: 424-428

Coauthor Index

1Nikitas A. Alexandridis [1] [2]
2Rohan Bafna [46]
3Tae-Gyu Chang [39]
4Anthony T. Chronopoulos [22]
5Kanchan Devarakonda [53]
6Alexandros V. Gerbessiotis [46]
7Haim Grebel [22]
8Nagasimha G. Haravu [5]
9Satchidanand G. Haridas [30]
10Muhammad Z. Hasan [38] [45] [48]
11Jie Hu [40] [42] [44] [47] [49] [50] [54] [56] [57] [58]
12Jie S. Hu [36]
13Segreen Ingersoll [24]
14Dejiang Jin [28] [31] [34] [52] [55]
15Johnsy K. John [36] [40]
16Sanjay Krishnamurthy [19]
17Xi Li [16] [18]
18Greg M. Link [40]
19Constantine N. Manikopoulos [16] [18]
20Florent Marcelli [22]
21Peter Meer [10]
22Arup Mukherjee [15]
23Paraskevi Papathanasiou [26]
24Roberto Rojas-Cessa [53]
25Devenkumar P. Shah [12]
26Muhammad A. Siddiqui [9]
27Michalis A. Sideras [14]
28P. D. Tsanakas [1]
29Qian Wang [20] [21] [26]
30Shuai Wang [40] [42] [44] [49] [50] [56] [57] [58]
31Xiaofang Wang [27] [32] [33] [37] [43] [51] [54]
32Xizhen Xu [29] [35] [39] [41]
33Hongyan Yang [47] [49] [50] [56]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)