Sudhakar Muddu

2008
19	EE	Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma: Defocus-Aware Leakage Estimation and Control. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 230-240 (2008)
2002
18	EE	Sudhakar Muddu: Estimation needs for future networking systems interconnect. SLIP 2002: 41-44
17	EE	Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky: Provably good global buffering by generalized multiterminalmulticommodity flow approximation. IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 263-274 (2002)
2001
16	EE	Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky: Provably good global buffering by multi-terminal multicommodity flow approximation. ASP-DAC 2001: 120-125
15	EE	Andrew B. Kahng, Sudhakar Muddu, Niranjan Pol, Devendra Vidhani: Noise Model for Multiple Segmented Coupled RC Interconnects. ISQED 2001: 145-150
14	EE	Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky: Practical Approximation Algorithms for Separable Packing Linear Programs. WADS 2001: 325-337
2000
13	EE	Andrew B. Kahng, Sudhakar Muddu, Egino Sarto: On switch factor based analysis of coupled RC interconnects. DAC 2000: 79-84
12		Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky: Provably Good Global Buffering Using an Available Buffer Block Plan. ICCAD 2000: 104-109
11		Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester: Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. ICCAD 2000: 56-61
1999
10		Andrew B. Kahng, Sudhakar Muddu, Egino Sarto: Interconnect Optimization Strategies for High-Performance VLSI Designs. VLSI Design 1999: 464-469
9	EE	Andrew B. Kahng, Sudhakar Muddu: Improved Effective Capacitance Computations for Use in Logic and Layout Optimization. VLSI Design 1999: 578-583
1998
8	EE	Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma: Interconnect Tuning Strategies for High-Performance Ics. DATE 1998: 471-478
7	EE	Andrew B. Kahng, Sudhakar Muddu: New efficient algorithms for computing effective capacitance. ISPD 1998: 147-151
1997
6	EE	Andrew B. Kahng, Sudhakar Muddu: Analysis of RC interconnections under ramp input. ACM Trans. Design Autom. Electr. Syst. 2(2): 168-192 (1997)
5	EE	Andrew B. Kahng, Sudhakar Muddu: An analytical delay model for RLC interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 16(12): 1507-1514 (1997)
1996
4	EE	Andrew B. Kahng, Sudhakar Muddu: Analysis of RC Interconnections Under Ramp Input. DAC 1996: 533-538
3	EE	Andrew B. Kahng, Kei Masuko, Sudhakar Muddu: Analytical delay models for VLSI interconnects under ramp input. ICCAD 1996: 30-36
1994
2	EE	Andrew B. Kahng, Sudhakar Muddu: Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model. DAC 1994: 563-569
1	EE	Sudhakar Muddu, Andrew B. Kahng: Optimal equivalent circuits for interconnect delay calculations using moments. EURO-DAC 1994: 164-169

Coauthor Index

1	Yu Cao	[11]
2	Feodor F. Dragan	[12] [14] [16] [17]
3	Chenming Hu	[11]
4	Xuejue Huang	[11]
5	Andrew B. Kahng	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [19]
6	Ion I. Mandoiu	[12] [14] [16] [17]
7	Kei Masuko	[3]
8	Niranjan Pol	[15]
9	Egino Sarto	[8] [10] [13]
10	Puneet Sharma	[19]
11	Rahul Sharma	[8]
12	Dirk Stroobandt	[11]
13	Dennis Sylvester	[11]
14	Devendra Vidhani	[15]
15	Alexander Zelikovsky	[12] [14] [16] [17]