| 2008 |
|---|
| 16 | EE | Karam S. Chatha,
Krishnan Srinivasan,
Goran Konjevod:
Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1425-1438 (2008) |
| 2007 |
|---|
| 15 | EE | Krishnan Srinivasan,
Karam S. Chatha,
Goran Konjevod:
Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms.
ASP-DAC 2007: 184-190 |
| 14 | EE | Christopher Ostler,
Karam S. Chatha,
Vijay Ramamurthi,
Krishnan Srinivasan:
ILP and heuristic techniques for system-level design on network processor architectures.
ACM Trans. Design Autom. Electr. Syst. 12(4): (2007) |
| 13 | EE | Krishnan Srinivasan,
Karam S. Chatha:
Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints.
Integration 40(3): 326-354 (2007) |
| 2006 |
|---|
| 12 | EE | Krishnan Srinivasan,
Karam S. Chatha:
Layout aware design of mesh based NoC architectures.
CODES+ISSS 2006: 136-141 |
| 11 | EE | Krishnan Srinivasan,
Karam S. Chatha:
A low complexity heuristic for design of custom network-on-chip architectures.
DATE 2006: 130-135 |
| 10 | EE | Krishnan Srinivasan,
Karam S. Chatha:
A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures.
ISQED 2006: 352-357 |
| 9 | EE | Krishnan Srinivasan,
Karam S. Chatha,
Goran Konjevod:
Linear-programming-based techniques for synthesis of network-on-chip architectures.
IEEE Trans. VLSI Syst. 14(4): 407-420 (2006) |
| 2005 |
|---|
| 8 | EE | Krishnan Srinivasan,
Karam S. Chatha:
SAGA: synthesis technique for guaranteed throughput NoC architectures.
ASP-DAC 2005: 489-494 |
| 7 | | Krishnan Srinivasan,
Karam S. Chatha,
Goran Konjevod:
An automated technique for topology and route generation of application specific on-chip interconnection networks.
ICCAD 2005: 231-237 |
| 6 | EE | Krishnan Srinivasan,
Karam S. Chatha:
A technique for low energy mapping and routing in network-on-chip architectures.
ISLPED 2005: 387-392 |
| 5 | EE | Krishnan Srinivasan,
Karam S. Chatha:
ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis.
VLSI Design 2005: 623-628 |
| 2004 |
|---|
| 4 | EE | Krishnan Srinivasan,
Karam S. Chatha,
Goran Konjevod:
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures.
ICCD 2004: 422-429 |
| 3 | EE | Krishnan Srinivasan,
Vijay Ramamurthi,
Karam S. Chatha:
A Technique for Energy versus Quality of Service Trade-Off for MPEG-2 Decoder.
ISVLSI 2004: 313-316 |
| 2 | EE | Krishnan Srinivasan,
Nagender Telkar,
Vijay Ramamurthi,
Karam S. Chatha:
System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures.
ISVLSI 2004: 39-45 |
| 1 | EE | Krishnan Srinivasan,
Karam S. Chatha:
An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures.
VLSI Design 2004: 255-260 |
