Jürgen Schlöffel

2008
15	EE	Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker: Resistive Bridging Fault Simulation of Industrial Circuits. DATE 2008: 628-633
14	EE	Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille: On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1329-1333 (2008)
2007
13	EE	Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers: Synthesis of irregular combinational functions with large don't care sets. ACM Great Lakes Symposium on VLSI 2007: 287-292
12	EE	Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel: Computation and Application of Absolute Dominators in Industrial Designs. European Test Symposium 2007: 137-144
11	EE	Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL 2007: 6
10	EE	Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. MEMOCODE 2007: 181-187
2006
9	EE	Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke: Fault detection and diagnosis with parity trees for space compaction of test responses. DAC 2006: 1095-1098
8	EE	Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers: Deterministic Logic BIST for Transition Fault Testing. European Test Symposium 2006: 123-130
7	EE	Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke: X-masking during logic BIST and its impact on defect coverage. IEEE Trans. VLSI Syst. 14(2): 193-202 (2006)
2005
6	EE	Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel: A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. Asian Test Symposium 2005: 22-27
5	EE	Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. ISVLSI 2005: 212-217
4	EE	Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel: ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips. VLSI Design 2005: 354-359
3	EE	Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel: Implementing a Scheme for External Deterministic Self-Test. VTS 2005: 101-106
2004
2	EE	Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel: Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model. DFT 2004: 174-182
2000
1	EE	Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel: PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. PATMOS 2000: 306-315

Coauthor Index

1	Walter Anheier	[2] [4] [6]
2	Erich Barke	[1]
3	Bernd Becker	[7] [15]
4	Rolf Drechsler	[5] [10] [11] [14]
5	Kishore K. Duganapalli	[6]
6	Stephan Eggersglüß	[10] [11] [14]
7	Piet Engelke	[7] [15]
8	Görschwin Fey	[5] [10] [11] [14]
9	Michael Garbers	[3] [8] [13]
10	Valentin Gherman	[3] [8] [13]
11	Andreas Glowatz	[5] [9] [10] [11] [12] [14]
12	Sandeep Kumar Goel	[9]
13	Abdul Wahid Hakmi	[3]
14	Friedrich Hapke	[5] [7] [9] [10] [11] [14]
15	Andreas Herrmann	[1]
16	Rene Krenz-Baath	[12]
17	R. D. Mascarenhas	[13]
18	Volker Meyer	[2] [4]
19	Ajoy Kumar Palit	[2] [4] [6]
20	Ilia Polian	[7] [15]
21	Junhao Shi	[5]
22	Mathias Silvant	[1]
23	Yuyi Tang	[7]
24	Daniel Tille	[11] [14]
25	Harald P. E. Vranken	[9]
26	Michael Wittke	[7]
27	Lei Wu	[6]
28	Hans-Joachim Wunderlich	[3] [7] [8] [13]

Colors in the list of coauthors