2009 |
53 | EE | Alessandro Cevrero,
Panagiotis Athanasopoulos,
Hadi Parandeh-Afshar,
Philip Brisk,
Yusuf Leblebici,
Paolo Ienne,
Maurizio Skerlj:
3D configuration caching for 2D FPGAs.
FPGA 2009: 286 |
52 | EE | Francesco Regazzoni,
Thomas Eisenbarth,
Axel Poschmann,
Johann Großschädl,
Frank K. Gürkaynak,
Marco Macchetti,
Zeynep Toprak Deniz,
Laura Pozzi,
Christof Paar,
Yusuf Leblebici,
Paolo Ienne:
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology.
Transactions on Computational Science 4: 230-243 (2009) |
2008 |
51 | EE | Seyed Hosein Attarzadeh Niaki,
Alessandro Cevrero,
Philip Brisk,
Chrysostomos Nicopoulos,
Frank K. Gürkaynak,
Yusuf Leblebici,
Paolo Ienne:
Design space exploration for field programmable compressor trees.
CASES 2008: 207-216 |
50 | EE | M. Haykel Ben Jamaa,
David Atienza,
Yusuf Leblebici,
Giovanni De Micheli:
Programmable logic circuits based on ambipolar CNFET.
DAC 2008: 339-340 |
49 | EE | Carlotta Guiducci,
Alexandre Schmid,
Frank K. Gürkaynak,
Yusuf Leblebici:
Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces.
DATE 2008: 1328-1333 |
48 | EE | Stéphane Badel,
Erdem Guleyupoglu,
Ozgur Inac,
Anna Pena Martinez,
Paolo Vietti,
Frank K. Gürkaynak,
Yusuf Leblebici:
A Generic Standard Cell Design Methodology for Differential Circuit Styles.
DATE 2008: 843-848 |
47 | EE | Alessandro Cevrero,
Panagiotis Athanasopoulos,
Hadi Parandeh-Afshar,
Ajay K. Verma,
Philip Brisk,
Frank K. Gürkaynak,
Yusuf Leblebici,
Paolo Ienne:
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.
FPGA 2008: 181-190 |
46 | EE | Armin Tajalli,
Frank K. Gürkaynak,
Yusuf Leblebici,
Massimo Alioto,
Elizabeth J. Brauer:
Improving the power-delay product in SCL circuits using source follower output stage.
ISCAS 2008: 145-148 |
45 | EE | Bahman Kheradmand Boroujeni,
Christian Piguet,
Yusuf Leblebici:
Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs.
PATMOS 2008: 11-20 |
44 | EE | Armin Tajalli,
Massimo Alioto,
Elizabeth J. Brauer,
Yusuf Leblebici:
Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits.
PATMOS 2008: 21-30 |
43 | EE | M. Haykel Ben Jamaa,
Kirsten E. Moselund,
David Atienza,
Didier Bouvet,
Adrian M. Ionescu,
Yusuf Leblebici,
Giovanni De Micheli:
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2053-2067 (2008) |
2007 |
42 | EE | Milos Stanisavljevic,
Frank K. Gürkaynak,
Alexandre Schmid,
Yusuf Leblebici,
Maria Gabrani:
Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density.
ACM Great Lakes Symposium on VLSI 2007: 204-207 |
41 | EE | M. Haykel Ben Jamaa,
Kirsten E. Moselund,
David Atienza,
Didier Bouvet,
Adrian M. Ionescu,
Yusuf Leblebici,
Giovanni De Micheli:
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays.
ICCAD 2007: 765-772 |
40 | EE | Francesco Regazzoni,
Stéphane Badel,
Thomas Eisenbarth,
Johann Großschädl,
Axel Poschmann,
Zeynep Toprak Deniz,
Marco Macchetti,
Laura Pozzi,
Christof Paar,
Yusuf Leblebici,
Paolo Ienne:
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies.
ICSAMOS 2007: 209-214 |
39 | EE | Stéphane Badel,
Yusuf Leblebici:
Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage.
ISCAS 2007: 1871-1874 |
38 | EE | Ilhan Hatirnaz,
Stéphane Badel,
Nuria Pazos,
Yusuf Leblebici,
Srinivasan Murali,
David Atienza,
Giovanni De Micheli:
Early wire characterization for predictable network-on-chip global interconnects.
SLIP 2007: 57-64 |
37 | EE | Paul Muller,
Armin Tajalli,
Seyed Mojtaba Atarodi,
Yusuf Leblebici:
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
CoRR abs/0710.4727: (2007) |
2006 |
36 | EE | Ayse Kivilcim Coskun,
Tajana Simunic Rosing,
Yusuf Leblebici,
Giovanni De Micheli:
A simulation methodology for reliability analysis in multi-core SoCs.
ACM Great Lakes Symposium on VLSI 2006: 95-99 |
35 | EE | Milos Stanisavljevic,
Alexandre Schmid,
Yusuf Leblebici:
Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density.
IJCNN 2006: 2771-2778 |
34 | EE | Armin Tajalli,
Paul Muller,
Seyed Mojtaba Atarodi,
Yusuf Leblebici:
Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs.
ISCAS 2006 |
33 | EE | Elizabeth J. Brauer,
Ilhan Hatirnaz,
Stéphane Badel,
Yusuf Leblebici:
Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design.
ISCAS 2006 |
32 | EE | O. C. Akgun,
Yusuf Leblebici:
Weak inversion performance of CMOS and DCVSPG logic families in sub-300 mV range.
ISCAS 2006 |
31 | EE | Derin Derin Harmanci,
Nuria Pazos,
Paolo Ienne,
Yusuf Leblebici:
A Predictable Communication Scheme for Embedded Multiprocessor Systems.
VLSI-SoC 2006: 152-157 |
30 | EE | Stéphane Badel,
Ilhan Hatirnaz,
Yusuf Leblebici,
Elizabeth J. Brauer:
Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells.
VLSI-SoC 2006: 234-238 |
29 | EE | Zeynep Toprak Deniz,
Yusuf Leblebici,
Eric A. Vittoz:
Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation.
VLSI-SoC 2006: 379-384 |
28 | EE | Ayse Kivilcim Coskun,
Tajana Simunic,
Kresimir Mihic,
Giovanni De Micheli,
Yusuf Leblebici:
Analysis and Optimization of MPSoC Reliability.
J. Low Power Electronics 2(1): 56-69 (2006) |
2005 |
27 | EE | Sorin Cotofana,
Alexandre Schmid,
Yusuf Leblebici,
Adrian M. Ionescu,
Oliver Soffke,
Peter Zipf,
Manfred Glesner,
A. Rubio:
CONAN - A Design Exploration Framework for Reliable Nano-Electronics.
ASAP 2005: 260-267 |
26 | EE | Paul Muller,
Armin Tajalli,
Seyed Mojtaba Atarodi,
Yusuf Leblebici:
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit.
DATE 2005: 258-263 |
25 | EE | Soner Yaldiz,
Alper Demir,
Serdar Tasiran,
Paolo Ienne,
Yusuf Leblebici:
Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems.
ESTImedia 2005: 135-140 |
24 | EE | Paul Muller,
Yusuf Leblebici:
Jitter Tolerance Analysis of Clock and Data Recovery Circuits.
FDL 2005: 143-147 |
23 | EE | Zeynep Toprak Deniz,
Yusuf Leblebici:
Low-power current mode logic for improved DPA-resistance in embedded systems.
ISCAS (2) 2005: 1059-1062 |
22 | EE | Mehmet Derin Harmanci,
Nuria Pazos Escudero,
Yusuf Leblebici,
Paolo Ienne:
Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip.
ISCAS (2) 2005: 1782-1785 |
21 | EE | Takahide Oya,
Tetsuya Asai,
Yoshihito Amemiya,
Alexandre Schmid,
Yusuf Leblebici:
Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture.
ISCAS (3) 2005: 2535-2538 |
20 | EE | Armin Tajalli,
Paul Muller,
Seyed Mojtaba Atarodi,
Yusuf Leblebici:
A low-power, multichannel gated oscillator-based CDR for short-haul applications.
ISLPED 2005: 107-110 |
19 | EE | Milos Stanisavljevic,
Alexandre Schmid,
Yusuf Leblebici:
A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis.
VLSI-SoC 2005: 111-125 |
18 | EE | Takahide Oya,
Alexandre Schmid,
Tetsuya Asai,
Yusuf Leblebici,
Yoshihito Amemiya:
On the fault tolerance of a clustered single-electron neural network for differential enhancement.
IEICE Electronic Express 2(3): 76-80 (2005) |
2004 |
17 | | Elizabeth J. Brauer,
Yusuf Leblebici:
Low noise MCML prefix adders using 0.18 µm CMOS technology.
Circuits, Signals, and Systems 2004: 467-470 |
16 | | Elizabeth J. Brauer,
Yusuf Leblebici:
Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic.
Circuits, Signals, and Systems 2004: 483-487 |
15 | EE | Alexandre Schmid,
Yusuf Leblebici:
A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies.
DFT 2004: 39-47 |
14 | EE | Alexandre Schmid,
Yusuf Leblebici:
Robust and fault-tolerant circuit design for nanometer-scale devices and single-electron transistors.
ISCAS (3) 2004: 685-688 |
13 | | Ilhan Hatirnaz,
Yusuf Leblebici:
Modelling and implementation of twisted differential on-chip interconnects for crosstalk noise reduction.
ISCAS (5) 2004: 185-188 |
12 | | Stéphane Badel,
Alexandre Schmid,
Yusuf Leblebici:
Mixed analog-digital image processing circuit based on Hamming artificial neural network architecture.
ISCAS (5) 2004: 780-783 |
11 | EE | Alexandre Schmid,
Yusuf Leblebici:
Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors.
IEEE Trans. VLSI Syst. 12(11): 1156-1166 (2004) |
2003 |
10 | EE | Stéphane Badel,
Alexandre Schmid,
Yusuf Leblebici:
VLSI Realization of a Two-Dimensional Hamming Distance Comparator ANN for Image Processing Applications.
ESANN 2003: 445-450 |
9 | EE | Zeynep Toprak Deniz,
Yusuf Leblebici:
Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology.
ISCAS (1) 2003: 841-844 |
8 | EE | Turan Demirci,
Ilhan Hatirnaz,
Yusuf Leblebici:
Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity.
ISCAS (5) 2003: 453-456 |
1999 |
7 | EE | Ilhan Hatirnaz,
Frank K. Gürkaynak,
Yusuf Leblebici:
Realization of a programmable rank-order filter architecture using capacitive threshold logic gates.
ISCAS (1) 1999: 435-438 |
6 | EE | Alexandre Schmid,
D. Bowler,
R. Baumgartner,
Yusuf Leblebici:
A novel analog-digital flash converter architecture based on capacitive threshold gates.
ISCAS (2) 1999: 172-175 |
1993 |
5 | EE | Yung-Ho Shih,
Yusuf Leblebici,
Sung-Mo Kang:
ILLIADS: a fast timing and reliability simulator for digital MOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(9): 1387-1402 (1993) |
1992 |
4 | EE | Yusuf Leblebici,
Sung-Mo Kang:
Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(2): 235-246 (1992) |
1991 |
3 | | Yung-Ho Shih,
Yusuf Leblebici,
Sung-Mo Kang:
New Simulation Methods for MOS VLSI Timing and Reliability.
ICCAD 1991: 162-165 |
2 | EE | Carlos H. Díaz,
Sung-Mo Kang,
Yusuf Leblebici:
An accurate analytical delay model for BiCMOS driver circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 577-588 (1991) |
1990 |
1 | | Yusuf Leblebici,
Sung-Mo Kang:
An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis.
ICCAD 1990: 400-403 |