dblp.uni-trier.dewww.uni-trier.de

Yusuf Leblebici

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo
Home Page

2009
53EEAlessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj: 3D configuration caching for 2D FPGAs. FPGA 2009: 286
52EEFrancesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne: Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. Transactions on Computational Science 4: 230-243 (2009)
2008
51EESeyed Hosein Attarzadeh Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Design space exploration for field programmable compressor trees. CASES 2008: 207-216
50EEM. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli: Programmable logic circuits based on ambipolar CNFET. DAC 2008: 339-340
49EECarlotta Guiducci, Alexandre Schmid, Frank K. Gürkaynak, Yusuf Leblebici: Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces. DATE 2008: 1328-1333
48EEStéphane Badel, Erdem Guleyupoglu, Ozgur Inac, Anna Pena Martinez, Paolo Vietti, Frank K. Gürkaynak, Yusuf Leblebici: A Generic Standard Cell Design Methodology for Differential Circuit Styles. DATE 2008: 843-848
47EEAlessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190
46EEArmin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer: Improving the power-delay product in SCL circuits using source follower output stage. ISCAS 2008: 145-148
45EEBahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici: Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs. PATMOS 2008: 11-20
44EEArmin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici: Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. PATMOS 2008: 21-30
43EEM. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli: Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2053-2067 (2008)
2007
42EEMilos Stanisavljevic, Frank K. Gürkaynak, Alexandre Schmid, Yusuf Leblebici, Maria Gabrani: Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density. ACM Great Lakes Symposium on VLSI 2007: 204-207
41EEM. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli: Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays. ICCAD 2007: 765-772
40EEFrancesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne: A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. ICSAMOS 2007: 209-214
39EEStéphane Badel, Yusuf Leblebici: Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage. ISCAS 2007: 1871-1874
38EEIlhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli: Early wire characterization for predictable network-on-chip global interconnects. SLIP 2007: 57-64
37EEPaul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici: Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit CoRR abs/0710.4727: (2007)
2006
36EEAyse Kivilcim Coskun, Tajana Simunic Rosing, Yusuf Leblebici, Giovanni De Micheli: A simulation methodology for reliability analysis in multi-core SoCs. ACM Great Lakes Symposium on VLSI 2006: 95-99
35EEMilos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici: Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density. IJCNN 2006: 2771-2778
34EEArmin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici: Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs. ISCAS 2006
33EEElizabeth J. Brauer, Ilhan Hatirnaz, Stéphane Badel, Yusuf Leblebici: Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design. ISCAS 2006
32EEO. C. Akgun, Yusuf Leblebici: Weak inversion performance of CMOS and DCVSPG logic families in sub-300 mV range. ISCAS 2006
31EEDerin Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici: A Predictable Communication Scheme for Embedded Multiprocessor Systems. VLSI-SoC 2006: 152-157
30EEStéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer: Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells. VLSI-SoC 2006: 234-238
29EEZeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz: Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation. VLSI-SoC 2006: 379-384
28EEAyse Kivilcim Coskun, Tajana Simunic, Kresimir Mihic, Giovanni De Micheli, Yusuf Leblebici: Analysis and Optimization of MPSoC Reliability. J. Low Power Electronics 2(1): 56-69 (2006)
2005
27EESorin Cotofana, Alexandre Schmid, Yusuf Leblebici, Adrian M. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, A. Rubio: CONAN - A Design Exploration Framework for Reliable Nano-Electronics. ASAP 2005: 260-267
26EEPaul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici: Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. DATE 2005: 258-263
25EESoner Yaldiz, Alper Demir, Serdar Tasiran, Paolo Ienne, Yusuf Leblebici: Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems. ESTImedia 2005: 135-140
24EEPaul Muller, Yusuf Leblebici: Jitter Tolerance Analysis of Clock and Data Recovery Circuits. FDL 2005: 143-147
23EEZeynep Toprak Deniz, Yusuf Leblebici: Low-power current mode logic for improved DPA-resistance in embedded systems. ISCAS (2) 2005: 1059-1062
22EEMehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne: Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. ISCAS (2) 2005: 1782-1785
21EETakahide Oya, Tetsuya Asai, Yoshihito Amemiya, Alexandre Schmid, Yusuf Leblebici: Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. ISCAS (3) 2005: 2535-2538
20EEArmin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici: A low-power, multichannel gated oscillator-based CDR for short-haul applications. ISLPED 2005: 107-110
19EEMilos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici: A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis. VLSI-SoC 2005: 111-125
18EETakahide Oya, Alexandre Schmid, Tetsuya Asai, Yusuf Leblebici, Yoshihito Amemiya: On the fault tolerance of a clustered single-electron neural network for differential enhancement. IEICE Electronic Express 2(3): 76-80 (2005)
2004
17 Elizabeth J. Brauer, Yusuf Leblebici: Low noise MCML prefix adders using 0.18 µm CMOS technology. Circuits, Signals, and Systems 2004: 467-470
16 Elizabeth J. Brauer, Yusuf Leblebici: Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic. Circuits, Signals, and Systems 2004: 483-487
15EEAlexandre Schmid, Yusuf Leblebici: A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies. DFT 2004: 39-47
14EEAlexandre Schmid, Yusuf Leblebici: Robust and fault-tolerant circuit design for nanometer-scale devices and single-electron transistors. ISCAS (3) 2004: 685-688
13 Ilhan Hatirnaz, Yusuf Leblebici: Modelling and implementation of twisted differential on-chip interconnects for crosstalk noise reduction. ISCAS (5) 2004: 185-188
12 Stéphane Badel, Alexandre Schmid, Yusuf Leblebici: Mixed analog-digital image processing circuit based on Hamming artificial neural network architecture. ISCAS (5) 2004: 780-783
11EEAlexandre Schmid, Yusuf Leblebici: Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors. IEEE Trans. VLSI Syst. 12(11): 1156-1166 (2004)
2003
10EEStéphane Badel, Alexandre Schmid, Yusuf Leblebici: VLSI Realization of a Two-Dimensional Hamming Distance Comparator ANN for Image Processing Applications. ESANN 2003: 445-450
9EEZeynep Toprak Deniz, Yusuf Leblebici: Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology. ISCAS (1) 2003: 841-844
8EETuran Demirci, Ilhan Hatirnaz, Yusuf Leblebici: Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity. ISCAS (5) 2003: 453-456
1999
7EEIlhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici: Realization of a programmable rank-order filter architecture using capacitive threshold logic gates. ISCAS (1) 1999: 435-438
6EEAlexandre Schmid, D. Bowler, R. Baumgartner, Yusuf Leblebici: A novel analog-digital flash converter architecture based on capacitive threshold gates. ISCAS (2) 1999: 172-175
1993
5EEYung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang: ILLIADS: a fast timing and reliability simulator for digital MOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(9): 1387-1402 (1993)
1992
4EEYusuf Leblebici, Sung-Mo Kang: Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation. IEEE Trans. on CAD of Integrated Circuits and Systems 11(2): 235-246 (1992)
1991
3 Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang: New Simulation Methods for MOS VLSI Timing and Reliability. ICCAD 1991: 162-165
2EECarlos H. Díaz, Sung-Mo Kang, Yusuf Leblebici: An accurate analytical delay model for BiCMOS driver circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 577-588 (1991)
1990
1 Yusuf Leblebici, Sung-Mo Kang: An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis. ICCAD 1990: 400-403

Coauthor Index

1O. C. Akgun [32]
2Massimo Alioto [44] [46]
3Yoshihito Amemiya [18] [21]
4Tetsuya Asai [18] [21]
5Seyed Mojtaba Atarodi [20] [26] [34] [37]
6Panagiotis Athanasopoulos [47] [53]
7David Atienza [38] [41] [43] [50]
8Stéphane Badel [10] [12] [30] [33] [38] [39] [40] [48]
9R. Baumgartner [6]
10Bahman Kheradmand Boroujeni [45]
11Didier Bouvet [41] [43]
12D. Bowler [6]
13Elizabeth J. Brauer [16] [17] [30] [33] [44] [46]
14Philip Brisk [47] [51] [53]
15Alessandro Cevrero [47] [51] [53]
16Ayse Kivilcim Coskun [28] [36]
17Sorin Cotofana (Sorin Dan Cotofana) [27]
18Alper Demir [25]
19Turan Demirci [8]
20Zeynep Toprak Deniz [9] [23] [29] [40] [52]
21Carlos H. Díaz [2]
22Thomas Eisenbarth [40] [52]
23Nuria Pazos Escudero [22]
24Maria Gabrani [42]
25Manfred Glesner [27]
26Johann Großschädl [40] [52]
27Carlotta Guiducci [49]
28Erdem Guleyupoglu [48]
29Frank K. Gürkaynak [7] [42] [46] [47] [48] [49] [51] [52]
30Derin Derin Harmanci [31]
31Mehmet Derin Harmanci [22]
32Ilhan Hatirnaz [7] [8] [13] [30] [33] [38]
33Paolo Ienne [22] [25] [31] [40] [47] [51] [52] [53]
34Ozgur Inac [48]
35Adrian M. Ionescu [27] [41] [43]
36M. Haykel Ben Jamaa [41] [43] [50]
37Sung-Mo Kang [1] [2] [3] [4] [5]
38Marco Macchetti [40] [52]
39Anna Pena Martinez [48]
40Giovanni De Micheli [28] [36] [38] [41] [43] [50]
41Kresimir Mihic [28]
42Kirsten E. Moselund [41] [43]
43Paul Muller [20] [24] [26] [34] [37]
44Srinivasan Murali [38]
45Seyed Hosein Attarzadeh Niaki [51]
46Chrysostomos Nicopoulos [51]
47Takahide Oya [18] [21]
48Christof Paar [40] [52]
49Hadi Parandeh-Afshar [47] [53]
50Nuria Pazos [31] [38]
51Christian Piguet [45]
52Axel Poschmann [40] [52]
53Laura Pozzi [40] [52]
54Francesco Regazzoni [40] [52]
55A. Rubio [27]
56Alexandre Schmid [6] [10] [11] [12] [14] [15] [18] [19] [21] [27] [35] [42] [49]
57Yung-Ho Shih [3] [5]
58Tajana Simunic (Tajana Simunic Rosing) [28] [36]
59Maurizio Skerlj [53]
60Oliver Soffke [27]
61Milos Stanisavljevic [19] [35] [42]
62Armin Tajalli [20] [26] [34] [37] [44] [46]
63Serdar Tasiran [25]
64Ajay K. Verma [47]
65Paolo Vietti [48]
66Eric A. Vittoz [29]
67Soner Yaldiz [25]
68Peter Zipf [27]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)