| |
| 2008 | ||
|---|---|---|
| 3 | EE | Hiran Tennakoon, Carl Sechen: Nonconvex Gate Delay Modeling and Delay Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1583-1594 (2008) |
| 2005 | ||
| 2 | EE | Hiran Tennakoon, Carl Sechen: Efficient and accurate gate sizing with piecewise convex delay models. DAC 2005: 807-812 |
| 2002 | ||
| 1 | EE | Hiran Tennakoon, Carl Sechen: Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. ICCAD 2002: 395-402 |
| 1 | Carl Sechen | [1] [2] [3] |