| |
| 2009 | ||
|---|---|---|
| 2 | EE | Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey: Yield evaluation of analog placement with arbitrary capacitor ratio. ISQED 2009: 179-184 |
| 2008 | ||
| 1 | EE | Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen-Ching Wu: Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2097-2101 (2008) |
| 1 | Ji-Jan Chen | [1] |
| 2 | Jwu-E Chen | [1] [2] |
| 3 | Liang-Chia Cheng | [1] |
| 4 | Chin-Long Wey | [1] [2] |
| 5 | Wen-Ching Wu | [1] |