| 2009 |
|---|
| 71 | EE | Kelageri Nagaraj,
Sandip Kundu:
Process variation mitigation via post silicon clock tuning.
ACM Great Lakes Symposium on VLSI 2009: 227-232 |
| 70 | EE | Spandana Remarsu,
Sandip Kundu:
On process variation tolerant low cost thermal sensor design in 32nm CMOS technology.
ACM Great Lakes Symposium on VLSI 2009: 487-492 |
| 69 | EE | Alodeep Sanyal,
Abhisek Pan,
Sandip Kundu:
A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits.
ACM Great Lakes Symposium on VLSI 2009: 529-534 |
| 68 | EE | Kunal P. Ganeshpure,
Ilia Polian,
Sandip Kundu,
Bernd Becker:
Reducing temperature variability by routing heat pipes.
ACM Great Lakes Symposium on VLSI 2009: 63-68 |
| 67 | EE | Omer Khan,
Sandip Kundu:
Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines.
HiPEAC 2009: 293-307 |
| 66 | EE | Alodeep Sanyal,
Abhisek Pan,
Sandip Kundu:
A study on impact of loading effect on capacitive crosstalk noise.
ISQED 2009: 696-701 |
| 65 | EE | Kunal P. Ganeshpure,
Sandip Kundu:
An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays.
VLSI Design 2009: 233-238 |
| 64 | EE | Alodeep Sanyal,
Kunal P. Ganeshpure,
Sandip Kundu:
An Improved Soft-Error Rate Measurement Technique.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 596-600 (2009) |
| 2008 |
|---|
| 63 | EE | Aswin Sreedhar,
Alodeep Sanyal,
Sandip Kundu:
On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits.
DATE 2008: 616-621 |
| 62 | EE | Sandip Kundu:
The Guiding Light for Chip Testing.
DDECS 2008: 1 |
| 61 | EE | Abhisek Pan,
James W. Tschanz,
Sandip Kundu:
A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuit.
DFT 2008: 343-351 |
| 60 | EE | Hyunbean Yi,
Sandip Kundu:
Core Test Wrapper Design to Reduce Test Application Time for Modular SoC Testing.
DFT 2008: 412-420 |
| 59 | EE | Omer Khan,
Sandip Kundu:
A framework for predictive dynamic temperature management of microprocessor systems.
ICCAD 2008: 258-263 |
| 58 | EE | Aswin Sreedhar,
Sandip Kundu:
Modeling and analysis of non-rectangular transistors caused by lithographic distortions.
ICCD 2008: 444-449 |
| 57 | EE | Alodeep Sanyal,
Sandip Kundu:
A Built-in Test and Characterization Method for Circuit Marginality Related Failures.
ISQED 2008: 838-843 |
| 56 | EE | Irith Pomeranz,
Sudhakar M. Reddy,
Sandip Kundu:
On Common-Mode Skewed-Load and Broadside Tests.
VLSI Design 2008: 151-156 |
| 55 | EE | Piet Engelke,
Ilia Polian,
Michel Renovell,
Sandip Kundu,
Bharath Seshadri,
Bernd Becker:
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 327-338 (2008) |
| 54 | EE | Ashesh Rastogi,
Kunal P. Ganeshpure,
Alodeep Sanyal,
Sandip Kundu:
On Composite Leakage Current Maximization.
J. Electronic Testing 24(4): 405-420 (2008) |
| 2007 |
|---|
| 53 | EE | Ashesh Rastogi,
Wei Chen,
Sandip Kundu:
On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method.
DAC 2007: 712-715 |
| 52 | EE | Kunal P. Ganeshpure,
Sandip Kundu:
Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults.
DATE 2007: 540-545 |
| 51 | EE | Aswin Sreedhar,
Sandip Kundu:
On modeling impact of sub-wavelength lithography on transistors.
ICCD 2007: 84-90 |
| 50 | EE | Alodeep Sanyal,
Sandip Kundu:
On Derating Soft Error Probability Based on Strength Filtering.
IOLTS 2007: 152-160 |
| 49 | EE | Alodeep Sanyal,
Kunal P. Ganeshpure,
Sandip Kundu:
Accelerating Soft Error Rate Testing Through Pattern Selection.
IOLTS 2007: 191-193 |
| 48 | EE | Ashesh Rastogi,
Kunal P. Ganeshpure,
Sandip Kundu:
A Study on Impact of Leakage Current on Dynamic Power.
ISCAS 2007: 1069-1072 |
| 47 | EE | Alodeep Sanyal,
Kunal P. Ganeshpure,
Sandip Kundu:
On Accelerating Soft-Error Detection by Targeted Pattern Generation.
ISQED 2007: 723-728 |
| 46 | EE | Ashesh Rastogi,
Wei Chen,
Alodeep Sanyal,
Sandip Kundu:
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect.
VLSI Design 2007: 583-588 |
| 45 | EE | Ilia Polian,
Alejandro Czutro,
Sandip Kundu,
Bernd Becker:
Power Droop Testing.
IEEE Design & Test of Computers 24(3): 276-284 (2007) |
| 2006 |
|---|
| 44 | EE | Sandip Kundu:
A design for failure analysis (DFFA) technique to ensure incorruptible signatures.
DATE 2006: 309-310 |
| 43 | EE | Kunal P. Ganeshpure,
Alodeep Sanyal,
Sandip Kundu:
A Pattern Generation Technique for Maximizing Power Supply Currents.
ICCD 2006 |
| 42 | EE | Ilia Polian,
Alejandro Czutro,
Sandip Kundu,
Bernd Becker:
Power Droop Testing.
ICCD 2006 |
| 41 | EE | Sandip Kundu,
Ilia Polian:
An Improved Technique for Reducing False Alarms Due to Soft Errors.
IOLTS 2006: 105-110 |
| 40 | EE | Debasis Mitra,
Subhasis Bhattacharjee,
Susmita Sur-Kolay,
Bhargab B. Bhattacharya,
Sujit T. Zachariah,
Sandip Kundu:
Test Pattern Generation for Power Supply Droop Faults.
VLSI Design 2006: 343-348 |
| 39 | EE | Sandip Kundu:
TTTC technical forum honoring Sudhakar M. Reddy.
IEEE Design & Test of Computers 23(2): 167 (2006) |
| 2005 |
|---|
| 38 | EE | Sandip Kundu,
Piet Engelke,
Ilia Polian,
Bernd Becker:
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
Asian Test Symposium 2005: 266-271 |
| 37 | EE | Ilia Polian,
Sandip Kundu,
Jean Marc Gallière,
Piet Engelke,
Michel Renovell,
Bernd Becker:
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.
VTS 2005: 343-348 |
| 36 | EE | Sandip Kundu,
Sujit T. Zachariah,
Yi-Shing Chang,
Chandra Tirumurti:
On modeling crosstalk faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1909-1915 (2005) |
| 2004 |
|---|
| 35 | EE | Chandra Tirumurti,
Sandip Kundu,
Susmita Sur-Kolay,
Yi-Shing Chang:
A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit.
DATE 2004: 1078-1083 |
| 34 | EE | Rob A. Rutenbar,
Li-C. Wang,
Kwang-Ting Cheng,
Sandip Kundu:
Static statistical timing analysis for latch-based pipeline designs.
ICCAD 2004: 468-472 |
| 33 | EE | Sandip Kundu,
T. M. Mak,
Rajesh Galivanche:
Trends in manufacturing test methods and their implications.
ITC 2004: 679-687 |
| 32 | | Rob Aitken,
Stefan Eichenberger,
Gary Maier,
Sandip Kundu,
Hank Walker:
ITC 2003 Roundtable: Design for Manufacturability.
IEEE Design & Test of Computers 21(2): 144-156 (2004) |
| 31 | EE | Irith Pomeranz,
Sandip Kundu,
Sudhakar M. Reddy:
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units.
IEEE Trans. Computers 53(1): 83-88 (2004) |
| 30 | EE | Irith Pomeranz,
Sudhakar M. Reddy,
Sandip Kundu:
On the characterization and efficient computation of hard-to-detect bridging faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1640-1649 (2004) |
| 29 | EE | Sandip Kundu:
Pitfalls of hierarchical fault simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 312-314 (2004) |
| 2003 |
|---|
| 28 | EE | Bill Grundmann,
Rajesh Galivanche,
Sandip Kundu:
Circuit and Platform Design Challenges in Technologies beyond 90nm.
DATE 2003: 10044-10049 |
| 27 | EE | Sujit T. Zachariah,
Yi-Shing Chang,
Sandip Kundu,
Chandra Tirumurti:
On Modeling Cross-Talk Faults.
DATE 2003: 10490-10495 |
| 26 | EE | Irith Pomeranz,
Sudhakar M. Reddy,
Sandip Kundu:
On the Characterization of Hard-to-Detect Bridging Faults.
DATE 2003: 11012-11019 |
| 25 | EE | Masao Naruse,
Irith Pomeranz,
Sudhakar M. Reddy,
Sandip Kundu:
On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding.
ITC 2003: 1060-1068 |
| 2002 |
|---|
| 24 | EE | Irith Pomeranz,
Sandip Kundu,
Sudhakar M. Reddy:
On output response compression in the presence of unknown output values.
DAC 2002: 255-258 |
| 2001 |
|---|
| 23 | EE | Jing-Jia Liou,
Kwang-Ting Cheng,
Sandip Kundu,
Angela Krstic:
Fast Statistical Timing Analysis By Probabilistic Event Propagation.
DAC 2001: 661-666 |
| 22 | EE | Sitaram Yadavalli,
Sandip Kundu:
On Fault-Simulation Through Embedded Memories On Large Industrial Designs.
VLSI Design 2001: 117-121 |
| 21 | EE | Sandip Kundu,
Sujit T. Zachariah,
Sanjay Sengupta,
Rajesh Galivanche:
Test Challenges in Nanometer Technologies.
J. Electronic Testing 17(3-4): 209-218 (2001) |
| 2000 |
|---|
| 20 | EE | Jing-Jia Liou,
Angela Krstic,
Kwang-Ting Cheng,
Deb Aditya Mukherjee,
Sandip Kundu:
Performance sensitivity analysis using statistical method and its applications to delay.
ASP-DAC 2000: 587-592 |
| 1999 |
|---|
| 19 | EE | Sreenivas Mandava,
Sreejit Chakravarty,
Sandip Kundu:
On Detecting Bridges Causing Timing Failures.
ICCD 1999: 400-406 |
| 1998 |
|---|
| 18 | | Anirudh Devgan,
Sandip Kundu:
Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial).
ASP-DAC 1998: 345 |
| 17 | EE | Sandip Kundu:
IDDQ Defect Detection in Deep Submicron CMOS ICs.
Asian Test Symposium 1998: 150-152 |
| 16 | EE | Sandip Kundu:
GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification.
ITC 1998: 372- |
| 1997 |
|---|
| 15 | EE | Sandip Kundu,
Uttam Ghoshal:
Inductance analysis of on-chip interconnects [deep submicron CMOS].
ED&TC 1997: 252-255 |
| 14 | EE | Anirudh Devgan,
Leon Stok,
Sandip Kundu:
Timing analysis and optimization: from devices to systems (tutorial).
ICCAD 1997 |
| 1995 |
|---|
| 13 | EE | Vishwani D. Agrawal,
Bernard Courtois,
Fumiyasu Hirose,
Sandip Kundu,
Chung-Len Lee,
Yinghua Min,
P. Pal Chaudhuri:
Panel: New Research Problems in the Emerging Test Technology.
Asian Test Symposium 1995: 189- |
| 1994 |
|---|
| 12 | EE | Jacob A. Abraham,
Sandip Kundu,
Janak H. Patel,
Manuel A. d'Abreu,
Bulent I. Dervisoglu,
Marc E. Levitt,
Hector R. Sucar,
Ron G. Walther:
Microprocessor Testing: Which Technique is Best? (Panel).
DAC 1994: 294 |
| 11 | EE | Daniel Brand,
Anthony D. Drumm,
Sandip Kundu,
Prakash Narain:
Incremental synthesis.
ICCAD 1994: 14-18 |
| 10 | | Sandip Kundu:
Multifault Testable Circuits Based on Binary Parity Diagrams.
ICCD 1994: 363-366 |
| 9 | EE | Leendert M. Huisman,
Sandip Kundu:
Highly Reliable Symmetric Networks.
IEEE Trans. Parallel Distrib. Syst. 5(1): 94-97 (1994) |
| 1993 |
|---|
| 8 | | Ankan K. Pramanick,
Sandip Kundu:
Design of Scan-Based Path-Delay-Testable Sequential Circuits.
ITC 1993: 962-971 |
| 1992 |
|---|
| 7 | | Sandip Kundu,
Leendert M. Huisman,
Indira Nair,
Vijay S. Iyengar,
Lakshmi N. Reddy:
A Small Test Generator for Large Designs.
ITC 1992: 30-40 |
| 1991 |
|---|
| 6 | EE | Sandip Kundu,
Sudhakar M. Reddy,
Niraj K. Jha:
Design of robustly testable combinational logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 1036-1048 (1991) |
| 1990 |
|---|
| 5 | EE | Sandip Kundu,
Sudhakar M. Reddy:
Embedded Totally Self-Checking Checkers: A Practical Design.
IEEE Design & Test of Computers 7(4): 5-12 (1990) |
| 4 | | Sandip Kundu,
Sudhakar M. Reddy:
On Symmetric Error Correcting and All Unidirectional Error Detecting Codes.
IEEE Trans. Computers 39(6): 752-761 (1990) |
| 3 | EE | Sandip Kundu,
Sudhakar M. Reddy:
Robust tests for parity trees.
J. Electronic Testing 1(3): 191-200 (1990) |
| 1989 |
|---|
| 2 | EE | Sandip Kundu:
Design of multioutput CMOS combinational logic circuits for robust testability.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(11): 1222-1226 (1989) |
| 1988 |
|---|
| 1 | | Sandip Kundu,
Sudhakar M. Reddy:
Robust Tests for Parity Trees.
ITC 1988: 680-687 |
