| 2009 |
| 14 | EE | Ayhan A. Mutlu,
Jiayong Le,
Ruben Molina,
Mustafa Celik:
Parametric analysis to determine accurate interconnect extraction corners for design performance.
ISQED 2009: 419-423 |
| 2008 |
| 13 | EE | Xin Li,
Jiayong Le,
Mustafa Celik,
Lawrence T. Pileggi:
Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1041-1054 (2008) |
| 2007 |
| 12 | EE | Ayhan A. Mutlu,
Kelvin J. Le,
Mustafa Celik,
Dar-sun Tsien,
Garry Shyu,
Long-Ching Yeh:
An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization.
ISQED 2007: 677-684 |
| 2005 |
| 11 | | Xin Li,
Jiayong Le,
Mustafa Celik,
Lawrence T. Pileggi:
Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations.
ICCAD 2005: 844-851 |
| 2001 |
| 10 | EE | Yi-Chang Lu,
Mustafa Celik,
Tak Young,
Lawrence T. Pileggi:
Min/max On-Chip Inductance Models and Delay Metrics.
DAC 2001: 341-346 |
| 1999 |
| 9 | EE | Emrah Acar,
Altan Odabasioglu,
Mustafa Celik,
Lawrence T. Pileggi:
S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric.
Great Lakes Symposium on VLSI 1999: 60-63 |
| 8 | EE | Altan Odabasioglu,
Mustafa Celik,
Lawrence T. Pileggi:
Practical considerations for passive reduction of RLC circuits.
ICCAD 1999: 214-220 |
| 7 | EE | Mustafa Celik,
Lawrence T. Pileggi:
Metrics and bounds for phase delay and signal attenuation in RC(L)clock trees.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 293-300 (1999) |
| 1998 |
| 6 | EE | Altan Odabasioglu,
Mustafa Celik,
Lawrence T. Pileggi:
PRIMA: passive reduced-order interconnect macromodeling algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 645-654 (1998) |
| 1997 |
| 5 | EE | Zhijiang He,
Mustafa Celik,
Lawrence T. Pileggi:
SPIE: Sparse Partial Inductance Extraction.
DAC 1997: 137-140 |
| 4 | EE | Altan Odabasioglu,
Mustafa Celik,
Lawrence T. Pileggi:
PRIMA: passive reduced-order interconnect macromodeling algorithm.
ICCAD 1997: 58-65 |
| 3 | EE | Mustafa Celik,
Andreas C. Cangellaris:
Simulation of multiconductor transmission lines using Krylov subspace order-reduction techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 485-496 (1997) |
| 1996 |
| 2 | EE | Mustafa Celik,
Andreas C. Cangellaris:
A general dispersive multiconductor transmission line model for interconnect simulation in SPICE.
ICCAD 1996: 563-568 |
| 1994 |
| 1 | | Mustafa Celik,
O. Ocali,
Mehmet Ali Tan,
Abdullah Atalar:
Improving AWE Accuracy Using Multipoint Padé Approximation.
ISCAS 1994: 379-382 |