dblp.uni-trier.dewww.uni-trier.de

Rajarshi Mukherjee

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2008
30EERajarshi Mukherjee, Song Liu, Seda Ogrenci Memik, Somsubhra Mondal: A high-level clustering algorithm targeting dual Vdd FPGAs. ACM Trans. Design Autom. Electr. Syst. 13(4): (2008)
29EESeda Ogrenci Memik, Rajarshi Mukherjee, Min Ni, Jieyi Long: Optimizing Thermal Sensor Allocation for Microprocessors. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 516-527 (2008)
28EEJieyi Long, Seda Ogrenci Memik, Gokhan Memik, Rajarshi Mukherjee: Thermal monitoring mechanisms for chip multiprocessors. TACO 5(2): (2008)
2006
27EERajarshi Mukherjee, Seda Ogrenci Memik: Systematic temperature sensor allocation and placement for microprocessors. DAC 2006: 542-547
26 Rajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci Memik: A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration Overhead. ERSA 2006: 56-62
25EERajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci Memik: Thermal sensor allocation and placement for reconfigurable systems. ICCAD 2006: 437-442
24EERajarshi Mukherjee, Seda Ogrenci Memik: Physical aware frequency selection for dynamic thermal management in multi-core systems. ICCAD 2006: 547-552
23EESomsubhra Mondal, Rajarshi Mukherjee, Seda Ogrenci Memik: Fine-grain thermal profiling and sensor insertion for FPGAs. ISCAS 2006
22EERajarshi Mukherjee, Seda Ogrenci Memik: An Integrated Approach to Thermal Management in High-Level Synthesis. IEEE Trans. VLSI Syst. 14(11): 1165-1174 (2006)
2005
21EERajarshi Mukherjee, Seda Ogrenci Memik: Evaluation of dual VDD fabrics for low power FPGAs. ASP-DAC 2005: 1240-1243
20EERajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik: Temperature-aware resource allocation and binding in high-level synthesis. DAC 2005: 196-201
19EERajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik: Peak temperature control and leakage reduction during binding in high level synthesis. ISLPED 2005: 251-256
18EEEren Kursun, Rajarshi Mukherjee, Seda Ogrenci Memik: Early Quality Assessment for Low Power Behavioral Synthesis. J. Low Power Electronics 1(3): 273-285 (2005)
2004
17EERajarshi Mukherjee, Seda Ogrenci Memik: Power Management for FPGAs: Power-Driven Design Partitioning. FCCM 2004: 326-327
16EERajarshi Mukherjee, Seda Ogrenci Memik: Power-Driven Design Partitioning. FPL 2004: 740-750
15EERajarshi Mukherjee, Alex K. Jones, Prithviraj Banerjee: Handling Data Streams while Compiling C Programs onto Hardware. ISVLSI 2004: 271-272
14EEIndradeep Ghosh, Rajarshi Mukherjee, Mukul R. Prasad, Masahiro Fujita: High Level Design Validation: Current Practices and Future Directions. VLSI Design 2004: 9-11
2003
13EEKelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee, Jawahar Jain: Solving the latch mapping problem in an industrial setting. DAC 2003: 442-447
2002
12EERajarshi Mukherjee, Yozo Nakayama, Toshiya Mima: Verification of an Industrial CC-NUMA Server. VLSI Design 2002: 747-
11 Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita: Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. Formal Methods in System Design 21(1): 95-101 (2002)
2001
10EEWanlin Cao, D. M. H. Walker, Rajarshi Mukherjee: An efficient solution to the storage correspondence problem for large sequential circuits. ASP-DAC 2001: 181-186
2000
9EERajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita: Automatic partitioning for efficient combinatorial verification. ASP-DAC 2000: 67-72
8EEVamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita: Hierarchical Error Diagnosis Targeting RTL Circuits. VLSI Design 2000: 436-441
7EEAnkur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao: Testing, Verification, and Diagnosis in the Presence of Unknowns. VTS 2000: 263-270
1999
6EEVamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni: Multiple Error Diagnosis Based on Xlists. DAC 1999: 660-665
5EERajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell: An Efficient Filter-Based Approach for Combinational Verification. DATE 1999: 132-137
4EERajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell: An efficient filter-based approach for combinational verification. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1542-1557 (1999)
1996
3EERajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell: On More Efficient Combinational ATPG Using Functional Learning. VLSI Design 1996: 107-110
1995
2EEJawahar Jain, Rajarshi Mukherjee, Masahiro Fujita: Advanced Verification Techniques Based on Learning. DAC 1995: 420-426
1993
1 Arjun Rajagopal, Belli Kuttanna, Balaji Janakiraman, Rajarshi Mukherjee, Joy Shetler: A Reconfigurable Arithmetic Processor. VLSI Design 1993: 172-175

Coauthor Index

1Jacob A. Abraham [3] [4] [5] [11]
2Prithviraj Banerjee (Prith Banerjee) [15]
3Pradeep Bollineni [6]
4Vamsi Boppana [6] [7] [8]
5Wanlin Cao [10]
6Masahiro Fujita [2] [3] [4] [5] [6] [7] [8] [9] [11] [14]
7Donald S. Fussell [3] [4] [5] [11]
8Indradeep Ghosh [8] [14]
9Michael S. Hsiao [7]
10Ankur Jain [7]
11Jawahar Jain [2] [3] [4] [5] [6] [7] [8] [9] [11] [13]
12Balaji Janakiraman [1]
13Alex K. Jones [15]
14Eren Kursun [18]
15Belli Kuttanna [1]
16Song Liu [30]
17Jieyi Long [28] [29]
18Gokhan Memik [19] [20] [28]
19Seda Ogrenci Memik (Seda Ogrenci) [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30]
20Toshiya Mima [12]
21Somsubhra Mondal [23] [25] [26] [30]
22Yozo Nakayama [12]
23Kelvin Ng [13]
24Min Ni [29]
25Mukul R. Prasad [13] [14]
26Arjun Rajagopal [1]
27Joy Shetler [1]
28Koichiro Takayama [4] [5] [9] [11]
29D. M. H. Walker (Duncan M. Hank Walker) [10]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)