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Dipankar Sarkar

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2008
8EEChandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar: An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 556-569 (2008)
2007
7EEChandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade: Hand-in-hand verification of high-level synthesis. ACM Great Lakes Symposium on VLSI 2007: 429-434
6EEChandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade: Register Sharing Verification During Data-Path Synthesis. ICCTA 2007: 135-140
5EEProdip Bhowal, Dipankar Sarkar, Siddhartha Mukhopadhyay, Anupam Basu: Fault diagnosis in discrete time hybrid systems - A case study. Inf. Sci. 177(5): 1290-1308 (2007)
2006
4EEChandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade: A Formal Verification Method of Scheduling in High-level Synthesis. ISQED 2006: 71-78
3EEChandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade: Verification of Scheduling in High-level Synthesis. ISVLSI 2006: 141-146
2004
2EEBatsayan Das, Dipankar Sarkar, Santanu Chattopadhyay: Model checking on state transition diagram. ASP-DAC 2004: 412-417
2000
1EEDipankar Sarkar: Status Condition Analysis during Data Path Verification of Sequential Circuits. VLSI Design 2000: 70-75

Coauthor Index

1Anupam Basu [5]
2Prodip Bhowal [5]
3Santanu Chattopadhyay [2]
4Batsayan Das [2]
5Chandan Karfa [3] [4] [6] [7] [8]
6P. Kumar [8]
7Chittaranjan A. Mandal (Chitta Mandal) [3] [4] [6] [7] [8]
8Siddhartha Mukhopadhyay [5]
9S. R. Pentakota [3] [4]
10Chris Reade [3] [4] [6] [7]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)