| 2008 |
|---|
| 8 | EE | Chandan Karfa,
Dipankar Sarkar,
Chitta Mandal,
P. Kumar:
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 556-569 (2008) |
| 2007 |
|---|
| 7 | EE | Chandan Karfa,
Dipankar Sarkar,
Chittaranjan A. Mandal,
Chris Reade:
Hand-in-hand verification of high-level synthesis.
ACM Great Lakes Symposium on VLSI 2007: 429-434 |
| 6 | EE | Chandan Karfa,
Chittaranjan A. Mandal,
Dipankar Sarkar,
Chris Reade:
Register Sharing Verification During Data-Path Synthesis.
ICCTA 2007: 135-140 |
| 5 | EE | Prodip Bhowal,
Dipankar Sarkar,
Siddhartha Mukhopadhyay,
Anupam Basu:
Fault diagnosis in discrete time hybrid systems - A case study.
Inf. Sci. 177(5): 1290-1308 (2007) |
| 2006 |
|---|
| 4 | EE | Chandan Karfa,
Chittaranjan A. Mandal,
Dipankar Sarkar,
S. R. Pentakota,
Chris Reade:
A Formal Verification Method of Scheduling in High-level Synthesis.
ISQED 2006: 71-78 |
| 3 | EE | Chandan Karfa,
Chittaranjan A. Mandal,
Dipankar Sarkar,
S. R. Pentakota,
Chris Reade:
Verification of Scheduling in High-level Synthesis.
ISVLSI 2006: 141-146 |
| 2004 |
|---|
| 2 | EE | Batsayan Das,
Dipankar Sarkar,
Santanu Chattopadhyay:
Model checking on state transition diagram.
ASP-DAC 2004: 412-417 |
| 2000 |
|---|
| 1 | EE | Dipankar Sarkar:
Status Condition Analysis during Data Path Verification of Sequential Circuits.
VLSI Design 2000: 70-75 |
