2008 |
30 | EE | Zhen Cao,
Tong Jing,
Jinjun Xiong,
Yu Hu,
Zhe Feng,
Lei He,
Xianlong Hong:
Fashion: A Fast and Accurate Solution to Global Routing Problem.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 726-737 (2008) |
2007 |
29 | EE | Zhen Cao,
Tong Jing,
Jinjun Xiong,
Yu Hu,
Lei He,
Xianlong Hong:
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm.
ASP-DAC 2007: 256-261 |
28 | EE | Chunta Chu,
Xinyi Zhang,
Lei He,
Tong Jing:
Temperature aware microprocessor floorplanning considering application dependent power load.
ICCAD 2007: 586-589 |
27 | EE | Yu Hu,
King Ho Tam,
Tong Jing,
Lei He:
Fast dual-vdd buffering based on interconnect prediction and sampling.
SLIP 2007: 95-102 |
2006 |
26 | EE | Zhen Cao,
Tong Jing,
Yu Hu,
Yiyu Shi,
Xianlong Hong,
Xiaodong Hu,
Guiying Yan:
DraXRouter: global routing in X-Architecture with dynamic resource assignment.
ASP-DAC 2006: 618-623 |
25 | EE | Yiyu Shi,
Tong Jing,
Lei He,
Zhe Feng,
Xianlong Hong:
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model.
ASP-DAC 2006: 630-635 |
24 | EE | S. P. Shang,
Xiaodong Hu,
Tong Jing:
Average lengths of wire routing under M-architecture and X-architecture.
ISCAS 2006 |
23 | EE | Zhe Feng,
Yu Hu,
Tong Jing,
Xianlong Hong,
Xiaodong Hu,
Guiying Yan:
An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane.
ISPD 2006: 48-55 |
22 | EE | Jingyu Xu,
Xianlong Hong,
Tong Jing,
Ling Zhang,
Jun Gu:
A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design.
Integration 39(4): 457-473 (2006) |
21 | EE | Yu Hu,
Tong Jing,
Zhe Feng,
Xianlong Hong,
Xiaodong Hu,
Guiying Yan:
ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm.
J. Comput. Sci. Technol. 21(1): 147-152 (2006) |
2005 |
20 | EE | Yang Yang,
Tong Jing,
Xianlong Hong,
Yu Hu,
Qi Zhu,
Xiaodong Hu,
Guiying Yan:
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield.
ASAP 2005: 198-203 |
19 | EE | Yin Wang,
Xianlong Hong,
Tong Jing,
Yang Yang,
Xiaodong Hu,
Guiying Yan:
The polygonal contraction heuristic for rectilinear Steiner tree construction.
ASP-DAC 2005: 1-6 |
18 | EE | Tong Jing,
Ling Zhang,
Jinghong Liang,
Jingyu Xu,
Xianlong Hong,
Jinjun Xiong,
Lei He:
A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem.
ASP-DAC 2005: 115-120 |
17 | EE | Yu Hu,
Tong Jing,
Xianlong Hong,
Zhe Feng,
Xiaodong Hu,
Guiying Yan:
An-OARSMan: obstacle-avoiding routing tree construction with good length performance.
ASP-DAC 2005: 7-12 |
16 | EE | Songpu Shang,
Xiaodong Hu,
Tong Jing:
Rotational Steiner Ratio Problem Under Uniform Orientation Metrics.
CJCDGCGT 2005: 166-176 |
15 | EE | Jingyu Xu,
Xianlong Hong,
Tong Jing:
Timing-driven global routing with efficient buffer insertion.
ISCAS (3) 2005: 2449-2452 |
14 | EE | Jingyu Xu,
Xianlong Hong,
Tong Jing,
Yang Yang:
Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design.
ISQED 2005: 616-621 |
13 | EE | Yu Hu,
Tong Jing,
Xianlong Hong,
Xiaodong Hu,
Guiying Yan:
A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design.
SAMOS 2005: 344-353 |
12 | EE | Qi Zhu,
Hai Zhou,
Tong Jing,
Xianlong Hong,
Yang Yang:
Spanning graph-based nonrectilinear steiner tree algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1066-1075 (2005) |
11 | EE | Jingyu Xu,
Xianlong Hong,
Tong Jing:
Timing-Driven Global Routing with Efficient Buffer Insertion.
IEICE Transactions 88-A(11): 3188-3195 (2005) |
2004 |
10 | EE | Jingyu Xu,
Xianlong Hong,
Tong Jing,
Ling Zhang,
Jun Gu:
A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design.
ASP-DAC 2004: 677-682 |
9 | EE | Qi Zhu,
Hai Zhou,
Tong Jing,
Xianlong Hong,
Yang Yang:
Efficient octilinear Steiner tree construction based on spanning graphs.
ASP-DAC 2004: 687-690 |
8 | | Ling Zhang,
Tong Jing,
Xianlong Hong,
Jingyu Xu,
Jinjun Xiong,
Lei He:
Performance and RLC crosstalk driven global routing.
ISCAS (5) 2004: 65-68 |
7 | EE | Yin Wang,
Xianlong Hong,
Tong Jing,
Yang Yang,
Xiaodong Hu,
Guiying Yan:
An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design.
PATMOS 2004: 442-452 |
6 | EE | Tong Jing,
Xianlong Hong,
Jingyu Xu,
Haiyun Bao,
Chung-Kuan Cheng,
Jun Gu:
UTACO: a unified timing and congestion optimization algorithm for standard cell global routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 358-365 (2004) |
2003 |
5 | EE | Jingyu Xu,
Xianlong Hong,
Tong Jing,
Yici Cai,
Jun Gu:
An efficient hierarchical timing-driven Steiner tree algorithm for global routing.
Integration 35(2): 69-84 (2003) |
4 | EE | Tong Jing,
Xianlong Hong,
Haiyun Bao,
Jingyu Xu,
Gu Jun:
SSTT: Efficient Local Search for GSI Global Routing.
J. Comput. Sci. Technol. 18(5): 632-640 (2003) |
3 | EE | Xianlong Hong,
Tong Jing,
Jingyu Xu,
Haiyun Bao,
Gu Jun:
CNB: A Critical-Network-Based Timing Optimization Method for Standard Cell Global Routing.
J. Comput. Sci. Technol. 18(6): 732-738 (2003) |
2002 |
2 | EE | Tong Jing,
Xianlong Hong,
Haiyun Bao,
Yici Cai,
Jingyu Xu,
Jun Gu:
A novel and efficient timing-driven global router for standard cell layout design based on critical network concept.
ISCAS (1) 2002: 165-168 |
1 | EE | Jingyu Xu,
Xianlong Hong,
Tong Jing,
Yici Cai,
Jun Gu:
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing.
VLSI Design 2002: 473-478 |