2008 | ||
---|---|---|
67 | EE | Hristo Nikolov, Mark Thompson, Todor Stefanov, Andy D. Pimentel, Simon Polstra, R. Bose, Claudiu Zissulescu, Ed F. Deprettere: Daedalus: toward composable multimedia MP-SoC design. DAC 2008: 574-579 |
66 | EE | Andy D. Pimentel, Todor Stefanov, Hristo Nikolov, Mark Thompson, Simon Polstra, Ed F. Deprettere: Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study. SAMOS 2008: 167-176 |
65 | EE | Hristo Nikolov, Todor Stefanov, Ed F. Deprettere: Systematic and Automated Multiprocessor System Design, Programming, and Implementation. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 542-555 (2008) |
64 | EE | Steven Derrien, Alexandru Turjan, Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere: Deriving efficient control in Process Networks with Compaan/Laura. IJES 3(3): 170-180 (2008) |
2007 | ||
63 | EE | Mark Thompson, Hristo Nikolov, Todor Stefanov, Andy D. Pimentel, Cagkan Erbas, Simon Polstra, Ed F. Deprettere: A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs. CODES+ISSS 2007: 9-14 |
62 | EE | Hristo Nikolov, Todor Stefanov, Ed F. Deprettere: Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips. FPL 2007: 580-584 |
61 | EE | Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: Classifying interprocess communication in process network representation of nested-loop programs. ACM Trans. Embedded Comput. Syst. 6(2): (2007) |
60 | EE | Ming-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Bart Kienhuis, Ed F. Deprettere: Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation. IEEE Transactions on Signal Processing 55(6-2): 3126-3138 (2007) |
2006 | ||
59 | EE | Ed F. Deprettere, Todor Stefanov, Shuvra S. Bhattacharyya, Mainak Sen: Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts. ASAP 2006: 186-190 |
58 | EE | Hristo Nikolov, Todor Stefanov, Ed F. Deprettere: Multi-processor system design with ESPAM. CODES+ISSS 2006: 211-216 |
57 | EE | Jérôme Lemaitre, Ed F. Deprettere: FPGA Implementation of a Prototype Hierarchical Control Network for Large-Scale Signal Processing Applications. Euro-Par 2006: 1192-1203 |
56 | EE | Hristo Nikolov, Todor Stefanov, Ed F. Deprettere: Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips. FPL 2006: 1-6 |
55 | EE | Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere: Requirements for Interfacing IP-Components in Re-configurable Platforms. VLSI Signal Processing 43(2-3): 173-184 (2006) |
2005 | ||
54 | EE | Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere: Expression Synthesis in Process Networks generated by LAURA. ASAP 2005: 15-21 |
53 | EE | Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere: Behavioral specification of control interface for signal processing applications. ASAP 2005: 43-49 |
52 | EE | Hristo Nikolov, Todor Stefanov, Ed F. Deprettere: Modeling and FPGA Implementation of Applications Using Parameterized Process Networks with Non-Static Parameters. FCCM 2005: 255-263 |
51 | Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere: Communication Synthesis in a multiprocessor environment. FPL 2005: 360-365 | |
50 | EE | Mihai-Lucian Cristea, Claudiu Zissulescu, Ed F. Deprettere, Herbert Bos: FPL-3E: Towards Language Support for Reconfigurable Packet Processing. SAMOS 2005: 82-92 |
49 | EE | Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: Solving Out-of-Order Communication in Kahn Process Networks. VLSI Signal Processing 40(1): 7-18 (2005) |
2004 | ||
48 | EE | Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks. ASAP 2004: 282-292 |
47 | EE | Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: Translating affine nested-loop programs to process networks. CASES 2004: 220-229 |
46 | EE | Todor Stefanov, Claudiu Zissulescu, Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: System Design Using Kahn Process Networks: The Compaan/Laura Approach. DATE 2004: 340-345 |
45 | EE | Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere: Increasing Pipelined IP Core Utilization in Process Networks Using Exploration. FPL 2004: 690-699 |
44 | EE | Sylvain Alliot, Ed F. Deprettere: Architecture Exploration of a Large Scale System. IEEE International Workshop on Rapid System Prototyping 2004: 217-224 |
43 | EE | Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere: On the (Re-)Use of IP-Components in Re-configurable Platforms. SAMOS 2004: 264-273 |
42 | EE | Ioan Cimpian, Alexandru Turjan, Ed F. Deprettere, Erwin A. de Kock: Communication Optimization in Compaan Process Networks. SAMOS 2004: 494-506 |
41 | EE | Laurentiu Nicolae, Ed F. Deprettere: Constraints Derivation and Propagation for Large-Scale Embedded Systems Exploration. SAMOS 2004: 550-560 |
40 | EE | Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: An Integer Linear Programming Approach to Classify the Communication in Process Networks. SCOPES 2004: 62-76 |
2003 | ||
39 | EE | Hylke W. van Dijk, Henk J. Sips, Ed F. Deprettere: Context-Aware Process Networks. ASAP 2003: 6-16 |
38 | EE | Todor Stefanov, Ed F. Deprettere: Deriving process networks from weakly dynamic applications in system-level design. CODES+ISSS 2003: 90-96 |
37 | EE | Vladimir D. Zivkovic, Erwin A. de Kock, Pieter van der Wolf, Ed F. Deprettere: Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs. DATE 2003: 10656-10661 |
36 | EE | Claudiu Zissulescu, Todor Stefanov, Bart Kienhuis, Ed F. Deprettere: Laura: Leiden Architecture Research and Exploration Tool. FPL 2003: 911-920 |
35 | EE | Bart Kienhuis, Ed F. Deprettere: Modeling Stream-Based Applications Using the SBF Model of Computation. VLSI Signal Processing 34(3): 291-300 (2003) |
2002 | ||
34 | Ed F. Deprettere, Jürgen Teich, Stamatis Vassiliadis: Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS Springer 2002 | |
33 | EE | Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere: A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks. ASAP 2002: 17-28 |
32 | EE | Todor Stefanov, Bart Kienhuis, Ed F. Deprettere: Algorithmic transformation techniques for efficient exploration of alternative application instances. CODES 2002: 7-12 |
31 | EE | Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers: A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach. Embedded Processor Design Challenges 2002: 18-37 |
30 | EE | Ed F. Deprettere, Edwin Rijpkema, Bart Kienhuis: Translating Imperative Affine Nested Loop Programs into Process Networks. Embedded Processor Design Challenges 2002: 89-111 |
2001 | ||
29 | EE | Paul Lieverse, Pieter van der Wolf, Ed F. Deprettere: A trace transformation technique for communication refinement. CODES 2001: 134-139 |
28 | EE | Paul Lieverse, Todor Stefanov, Pieter van der Wolf, Ed F. Deprettere: System Level Design with Spade: an M-JPEG Case Study. ICCAD 2001: 31-38 |
27 | EE | Andy D. Pimentel, Louis O. Hertzberger, Paul Lieverse, Pieter van der Wolf, Ed F. Deprettere: Exploring Embedded-Systems Architectures with Artemis. IEEE Computer 34(11): 57-63 (2001) |
26 | EE | Paul Lieverse, Pieter van der Wolf, Kees A. Vissers, Ed F. Deprettere: A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems. VLSI Signal Processing 29(3): 197-207 (2001) |
2000 | ||
25 | EE | Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, Bart Kienhuis: High Level Modeling for Parallel Executions of Nested Loop Algorithms. ASAP 2000: 79-91 |
24 | EE | Bart Kienhuis, Edwin Rijpkema, Ed F. Deprettere: Compaan: deriving process networks from Matlab for embedded signal processing architectures. CODES 2000: 13-17 |
23 | Edwin Rijpkema, Ed F. Deprettere, Bart Kienhuis: Deriving Process Networks from Nested Loop Algorithms. Parallel Processing Letters 10(2/3): 165-176 (2000) | |
22 | EE | Kees-Jan Van der Kolk, Jeong-A. Lee, Ed F. Deprettere: A Floating Point Vectoring Algorithm Based on Fast Rotations. VLSI Signal Processing 25(2): 125-139 (2000) |
21 | EE | Gerben J. Hekstra, Ed F. Deprettere, Jeong-A. Lee: Guest Editor's Introduction. VLSI Signal Processing 25(2): 99-100 (2000) |
1999 | ||
20 | EE | Kees-Jan Van der Kolk, Ed F. Deprettere, Jeong-A. Lee: A Floating Point Vectoring Algorithm Based on Fast Rotations. EUROMICRO 1999: 1140- |
19 | EE | Jun Ma, Keshab K. Parhi, Ed F. Deprettere: Derivation of parallel and pipelined orthogonal filter architectures via algorithm transformations. ISCAS (3) 1999: 347-350 |
18 | EE | Paul Lieverse, Ed F. Deprettere, Bart Kienhuis, Erwin A. de Kock: A Clustering Approach to Explore Grain-Sizes in the Definition of Processing Elements in Dataflow Architectures. VLSI Signal Processing 22(1): 9-20 (1999) |
1998 | ||
17 | EE | Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf: The construction of a retargetable simulator for an architecture template. CODES 1998: 125-129 |
16 | EE | Laurens Bierens, Ed F. Deprettere: Efficient Partitioning of Algorithms for Long Convolutions and their Mapping onto Architectures. VLSI Signal Processing 18(1): 51-64 (1998) |
1997 | ||
15 | EE | Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf: An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures. ASAP 1997: 338-349 |
14 | EE | Edwin Rijpkema, Gerben J. Hekstra, Ed F. Deprettere, Jun Ma: A strategy for determining a Jacobi specific dataflow processor. ASAP 1997: 53- |
13 | EE | Gerben J. Hekstra, Ed F. Deprettere: Fast Rotations: Low-cost Arithmetic Methods for Orthonormal Rotation. IEEE Symposium on Computer Arithmetic 1997: 116-125 |
1996 | ||
12 | EE | Hylke W. van Dijk, Gerben J. Hekstra, Ed F. Deprettere: Jacobi-Specific Processor Arrays. ASAP 1996: 323- |
11 | EE | Marc Moonen, Ed F. Deprettere: A fully pipelined RLS-based array for channel equalization. VLSI Signal Processing 14(1): 67-74 (1996) |
1995 | ||
10 | EE | Li-Sheng Shen, Ed F. Deprettere, Patrick Dewilde: A parallel image-rendering algorithm and architecture based on ray tracing and radiosity shading. Computers & Graphics 19(2): 281-296 (1995) |
1994 | ||
9 | Francky Catthoor, Ed F. Deprettere, Yu Hen Hu, Jan M. Rabaey, Heinrich Meyr, Lothar Thiele: Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures. ISCAS 1994: 129-136 | |
1993 | ||
8 | EE | Gerben J. Hekstra, Ed F. Deprettere: Floating point Cordic. IEEE Symposium on Computer Arithmetic 1993: 130-137 |
1991 | ||
7 | Li-Sheng Shen, F. A. J. Laarakker, Ed F. Deprettere: Space Partitioning for Mapping Radiosity Computations onto a Pipelined Parallel Architecture (II). Advances in Computer Graphics Hardware (Machines) 1991: 175-190 | |
6 | EE | Ed F. Deprettere: Introduction. VLSI Signal Processing 3(3): 149 (1991) |
1989 | ||
5 | A. C. Yilmaz, S. Hagestein, Ed F. Deprettere, Patrick Dewilde: A Hardware Algorithm for Fast Realistic Image Synthesis. Advances in Computer Graphics Hardware 1989: 37-60 | |
4 | EE | A. J. van der Hoeven, A. A. de Lange, Ed F. Deprettere, Patrick Dewilde: A New Model for the High Level Description and Simulation of VLSI Networks. DAC 1989: 738-741 |
3 | Jichun Bu, Ed F. Deprettere: A VLSI system architecture for high-speed radiative transfer 3D image synthesis. The Visual Computer 5(3): 121-133 (1989) | |
2 | EE | Paul F. C. Krekel, Ed F. Deprettere: A systolic algorithm and architecture for solving sets of linear equations with multi-band coefficient matrix. VLSI Signal Processing 1(2): 143-152 (1989) |
1988 | ||
1 | K. Jainandunsing, Ed F. Deprettere: Design of a Concurrent Computer for Solving Systems of Linear Equations. ISCA 1988: 204-211 |