| 2008 |
|---|
| 5 | EE | Dong Xiang,
Yang Zhao,
K. Chakrabarty,
Hideo Fujiwara:
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 999-1012 (2008) |
| 2007 |
|---|
| 4 | EE | I. O'Connor,
B. Courtois,
K. Chakrabarty,
N. Delorme,
M. Hampton,
J. Hartung:
Heterogeneous systems on chip and systems in package.
DATE 2007: 737-742 |
| 2005 |
|---|
| 3 | EE | Hosam M. F. AboElFotoh,
S. S. Iyengar,
K. Chakrabarty:
Computing reliability and message delay for Cooperative wireless distributed sensor networks subject to random failures.
IEEE Transactions on Reliability 54(1): 145-155 (2005) |
| 2003 |
|---|
| 2 | EE | K. Chakrabarty:
A synthesis-for-transparency approach for hierarchical and system-on-a-chip test.
IEEE Trans. VLSI Syst. 11(2): 167-179 (2003) |
| 1999 |
|---|
| 1 | EE | Paulo F. Flores,
Horácio C. Neto,
K. Chakrabarty,
João P. Marques Silva:
Test pattern generation for width compression in BIST.
ISCAS (1) 1999: 114-118 |
