K. Chakrabarty

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5EEDong Xiang, Yang Zhao, K. Chakrabarty, Hideo Fujiwara: A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 999-1012 (2008)
4EEI. O'Connor, B. Courtois, K. Chakrabarty, N. Delorme, M. Hampton, J. Hartung: Heterogeneous systems on chip and systems in package. DATE 2007: 737-742
3EEHosam M. F. AboElFotoh, S. S. Iyengar, K. Chakrabarty: Computing reliability and message delay for Cooperative wireless distributed sensor networks subject to random failures. IEEE Transactions on Reliability 54(1): 145-155 (2005)
2EEK. Chakrabarty: A synthesis-for-transparency approach for hierarchical and system-on-a-chip test. IEEE Trans. VLSI Syst. 11(2): 167-179 (2003)
1EEPaulo F. Flores, Horácio C. Neto, K. Chakrabarty, João P. Marques Silva: Test pattern generation for width compression in BIST. ISCAS (1) 1999: 114-118

Coauthor Index

1Hosam M. F. AboElFotoh [3]
2B. Courtois [4]
3N. Delorme [4]
4Paulo F. Flores [1]
5Hideo Fujiwara [5]
6M. Hampton [4]
7J. Hartung [4]
8S. S. Iyengar [3]
9Horácio C. Neto [1]
10I. O'Connor [4]
11João P. Marques Silva (João Marques-Silva) [1]
12Dong Xiang [5]
13Yang Zhao [5]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)