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Steven M. Nowick

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2008
57EECheoljoo Jeong, Steven M. Nowick: Technology Mapping and Cell Merger for Asynchronous Threshold Networks. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 659-672 (2008)
2007
56EECheoljoo Jeong, Steven M. Nowick: Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation. ASP-DAC 2007: 622-627
55EEMelinda Y. Agyekum, Steven M. Nowick: A Cycle-Based Decomposition Method for Burst-Mode Asynchronous Controllers. ASYNC 2007: 129-142
54EEAmitava Mitra, William F. McLaughlin, Steven M. Nowick: Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication. ASYNC 2007: 186-195
53EEPeggy B. McGee, Steven M. Nowick: An efficient algorithm for time separation of events in concurrent systems. ICCAD 2007: 180-187
52EEMontek Singh, Steven M. Nowick: The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style. IEEE Trans. VLSI Syst. 15(11): 1256-1269 (2007)
51EEMontek Singh, Steven M. Nowick: The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style. IEEE Trans. VLSI Syst. 15(11): 1270-1283 (2007)
50EEMontek Singh, Steven M. Nowick: MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines. IEEE Trans. VLSI Syst. 15(6): 684-698 (2007)
2006
49EECheoljoo Jeong, Steven M. Nowick: Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks. ASYNC 2006: 128-137
2005
48EEPeggy B. McGee, Steven M. Nowick, Edward G. Coffman Jr.: Efficient performance analysis of asynchronous systems based on periodicity. CODES+ISSS 2005: 225-230
47EEPeggy B. McGee, Steven M. Nowick: A lattice-based framework for the classification and design of asynchronous pipelines. DAC 2005: 491-496
2004
46EECheoljoo Jeong, Steven M. Nowick: Fast hazard detection in combinational circuits. DAC 2004: 592-595
45EETiberiu Chelcea, Steven M. Nowick: Robust interfaces for mixed-timing systems. IEEE Trans. VLSI Syst. 12(8): 857-873 (2004)
2003
44EESteven M. Nowick, Charles W. O'Donnell: On the Existence of Hazard-Free Multi-Level Logic. ASYNC 2003: 109-120
43EEYee William Li, George Patounakis, Anup Jose, Kenneth L. Shepard, Steven M. Nowick: Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application. ASYNC 2003: 216-226
42EESoha Hassoun, Steven M. Nowick, Leon Stok: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 662-664 (2003)
2002
41EEJosé A. Tierno, Sergey Rylov, Alexander Rylyakov, Montek Singh, Steven M. Nowick: An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz. ASYNC 2002: 84-
40EETiberiu Chelcea, Steven M. Nowick: Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems. DAC 2002: 405-410
39EERecep O. Ozdag, Peter A. Beerel, Montek Singh, Steven M. Nowick: High-Speed Non-Linear Asynchronous Pipelines. DATE 2002: 1000-1007
38EETiberiu Chelcea, Steven M. Nowick, Andrew Bardsley, Doug Edwards: A Burst-Mode Oriented Back-End for the Balsa Synthesis System. DATE 2002: 330-337
37 Tiberiu Chelcea, Steven M. Nowick: Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous Systems. IWLS 2002: 355-360
2001
36EETiberiu Chelcea, Steven M. Nowick: Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols. DAC 2001: 21-26
35EEMichael Theobald, Steven M. Nowick: Transformations for the Synthesis and Optimization of Asynchronous Distributed Control. DAC 2001: 263-268
34 Montek Singh, Steven M. Nowick: MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines. ICCD 2001: 9-17
2000
33EEMontek Singh, Steven M. Nowick: High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths. ASYNC 2000: 198-
32EETiberiu Chelcea, Steven M. Nowick: Low-Latency Asynchronous FIFO's Using Token Rings. ASYNC 2000: 210-
31EEMontek Singh, Steven M. Nowick: Synthesis for logical initializability of synchronous finite-state machines. IEEE Trans. VLSI Syst. 8(5): 542-557 (2000)
1999
30EEErik Brunvand, Steven M. Nowick, Kenneth Y. Yun: Practical Advances in Asynchronous Design and in Asynchronous/Synchronous Interfaces. DAC 1999: 104-109
29EERobert M. Fuhrer, Steven M. Nowick: OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic. ICCAD 1999: 7-13
1998
28EEMartin Benes, Steven M. Nowick, Andrew Wolfe: A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors. ASYNC 1998: 43-
27EEMichael Theobald, Steven M. Nowick: An Implicit Method for Hazard-Free Two-Level Logic Minimization. ASYNC 1998: 58-69
26EELuis A. Plana, Steven M. Nowick: Architectural optimization for low-power nonpipelined asynchronous systems. IEEE Trans. VLSI Syst. 6(1): 56-65 (1998)
25EEMichael Theobald, Steven M. Nowick: Fast heuristic and exact algorithms for two-level hazard-free logic minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1130-1147 (1998)
1997
24EEMartin Benes, Andrew Wolfe, Steven M. Nowick: A High-Speed Asynchronous Decompression Circuit for Embedded Processors. ARVLSI 1997: 219-237
23EESteven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel: Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders. ASYNC 1997: 210-
22EERobert M. Fuhrer, Steven M. Nowick: OPTIMIST: state minimization for optimal 2-level logic implementation. ICCAD 1997: 308-315
21 Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun: Practical Advances in Asynchronous Design. ICCD 1997: 662-668
20EESteven M. Nowick, Michael Theobald: Synthesis of low-power asynchronous circuits in a specified environment. ISLPED 1997: 92-95
19EEMontek Singh, Steven M. Nowick: Synthesis for Logical Initializability of Synchronous Finite State Machines. VLSI Design 1997: 76-81
18EESteven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng: Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. IEEE Trans. on CAD of Integrated Circuits and Systems 16(12): 1514-1521 (1997)
1996
17EEMichael Theobald, Steven M. Nowick, Tao Wu: Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic. DAC 1996: 71-76
16EEPrabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson, Steven M. Nowick: Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes. DAC 1996: 77-82
15EELuis A. Plana, Steven M. Nowick: Concurrency-oriented optimization for low-power asynchronous systems. ISLPED 1996: 151-156
14 Montek Singh, Steven M. Nowick: Synthesis-for-Initializability of Asynchronous Sequential Machines. ITC 1996: 232-241
1995
13EERobert M. Fuhrer, Bill Lin, Steven M. Nowick: Algorithms for the optimal state assignment of asynchronous state machines. ARVLSI 1995: 59-75
12EEPeter A. Beerel, Kenneth Y. Yun, Steven M. Nowick, Pei-Chuan Yeh: Estimation and bounding of energy consumption in burst-mode control circuits. ICCAD 1995: 26-33
11EERobert M. Fuhrer, Bill Lin, Steven M. Nowick: Symbolic hazard-free minimization and encoding of asynchronous finite state machines. ICCAD 1995: 604-611
10EESteven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng: Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. VLSI Design 1995: 171-176
9EESteven M. Nowick, David L. Dill: Exact two-level minimization of hazard-free logic with multiple-input changes. IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 986-997 (1995)
1994
8 Steven M. Nowick, Bill Coates: UCLOCK: Automated Design of High-Peformance Unclocked State Machines. ICCD 1994: 434-441
7EEGanesh Gopalakrishnan, Erik Brunvand, Nick Michell, Steven M. Nowick: A correctness criterion for asynchronous circuit validation and optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 13(11): 1309-1318 (1994)
1992
6EESteven M. Nowick, David L. Dill: Exact two-level minimization of hazard-free logic with multiple-input changes. ICCAD 1992: 626-630
5 Steven M. Nowick, Kenneth Y. Yun, David L. Dill: Practical Asynchronous Controller Design. ICCD 1992: 341-345
4 Kenneth Y. Yun, David L. Dill, Steven M. Nowick: Synthesis of 3D Asynchronous State Machines. ICCD 1992: 346-350
3 David L. Dill, Steven M. Nowick, Robert F. Sproull: Specification and Automatic Verification of Self-Timed Queues. Formal Methods in System Design 1(1): 29-60 (1992)
1991
2 Steven M. Nowick, David L. Dill: Automatic Synthesis of Locally-Clocked Asynchronous State Machines. ICCAD 1991: 318-321
1 Steven M. Nowick, David L. Dill: Synthesis of Asynchronous State Machines Using A Local Clock. ICCD 1991: 192-197

Coauthor Index

1Melinda Y. Agyekum [55]
2Andrew Bardsley [38]
3Peter A. Beerel [12] [23] [39]
4Martin Benes [24] [28]
5Erik Brunvand [7] [21] [30]
6Tiberiu Chelcea [32] [36] [37] [38] [40] [45]
7Fu-Chiung Cheng [10] [18]
8Bill Coates [8]
9Edward G. Coffman Jr. [48]
10David L. Dill [1] [2] [3] [4] [5] [6] [9]
11Ayoob E. Dooply [23]
12Doug Edwards [38]
13Robert M. Fuhrer [11] [13] [22] [29]
14Ganesh Gopalakrishnan [7] [16]
15Soha Hassoun [42]
16Hans M. Jacobson [16]
17Cheoljoo Jeong [46] [49] [56] [57]
18Niraj K. Jha [10] [18]
19Anup Jose [43]
20Prabhakar Kudva [16]
21Yee William Li [43]
22Bill Lin [11] [13]
23Peggy B. McGee [47] [48] [53]
24William F. McLaughlin [54]
25Nick Michell [7]
26Amitava Mitra [54]
27Charles W. O'Donnell [44]
28Recep O. Ozdag [39]
29George Patounakis [43]
30Luis A. Plana [15] [26]
31Sergey Rylov [41]
32Alexander Rylyakov [41]
33Kenneth L. Shepard [43]
34Montek Singh [14] [19] [31] [33] [34] [39] [41] [50] [51] [52]
35Robert F. Sproull [3]
36Leon Stok [42]
37Michael Theobald [17] [20] [25] [27] [35]
38José A. Tierno [41]
39Andrew Wolfe [24] [28]
40Tao Wu [17]
41Pei-Chuan Yeh [12]
42Kenneth Y. Yun [4] [5] [12] [21] [23] [30]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)