| 2008 |
|---|
| 5 | EE | David Walter,
Scott Little,
Chris J. Myers,
Nicholas Seegmiller,
Tomohiro Yoneda:
Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2223-2235 (2008) |
| 2007 |
|---|
| 4 | EE | David Walter,
Scott Little,
Nicholas Seegmiller,
Chris J. Myers,
Tomohiro Yoneda:
Symbolic Model Checking of Analog/Mixed-Signal Circuits.
ASP-DAC 2007: 316-323 |
| 2006 |
|---|
| 3 | EE | Scott Little,
Nicholas Seegmiller,
David Walter,
Chris J. Myers,
Tomohiro Yoneda:
Verification of analog/mixed-signal circuits using labeled hybrid petri nets.
ICCAD 2006: 275-282 |
| 2 | EE | Chris J. Myers,
Reid R. Harrison,
David Walter,
Nicholas Seegmiller,
Scott Little:
The Case for Analog Circuit Verification.
Electr. Notes Theor. Comput. Sci. 153(3): 53-63 (2006) |
| 2004 |
|---|
| 1 | EE | Scott Little,
David Walter,
Nicholas Seegmiller,
Chris J. Myers,
Tomohiro Yoneda:
Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets.
ATVA 2004: 426-440 |
