H.-S. Philip Wong

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8EENishant Patil, Jie Deng, Albert Lin, H.-S. Philip Wong, Subhasish Mitra: Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1725-1736 (2008)
7EEJie Deng, Albert Lin, Gordon C. Wan, H.-S. Philip Wong: Carbon nanotube transistor compact model for circuit design and performance optimization. JETC 4(2): (2008)
6EENishant Patil, Jie Deng, H.-S. Philip Wong, Subhasish Mitra: Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits. DAC 2007: 958-961
5EEJie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S. Philip Wong: Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI. ISQED 2007: 145-152
4EEH.-S. Philip Wong, Jie Deng, Arash Hazeghi, Tejas Krishnamohan, Gordon C. Wan: Carbon nanotube transistor circuits: models and tools for design and performance optimization. ICCAD 2006: 651-654
3EEH.-S. Philip Wong: Device and Technology Challenges for Nanoscale CMOS. ISQED 2006: 515-518
2EEH.-S. Philip Wong: Beyond the conventional transistor. IBM Journal of Research and Development 46(2-3): 133-168 (2002)
1 Yuan Taur, Yuh-Jier Mii, David J. Frank, H.-S. Philip Wong, Douglas A. Buchanan, Shalom J. Wind, Stephen A. Rishton, Watson A. Sai-Halasz, Edward J. Nowak: CMOS scaling into the 21st century: 0.1 µm and beyond. IBM Journal of Research and Development 39(1-2): 245-260 (1995)

Coauthor Index

1Douglas A. Buchanan [1]
2Ching-Te Chuang [5]
3Jie Deng [4] [5] [6] [7] [8]
4David J. Frank [1]
5Arash Hazeghi [4]
6Keunwoo Kim [5]
7Tejas Krishnamohan [4]
8Albert Lin [7] [8]
9Yuh-Jier Mii [1]
10Subhasish Mitra [6] [8]
11Edward J. Nowak [1]
12Nishant Patil [6] [8]
13Stephen A. Rishton [1]
14Watson A. Sai-Halasz [1]
15Yuan Taur [1]
16Gordon C. Wan [4] [7]
17Shalom J. Wind [1]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)