D. Michael Miller

2008
40	EE	David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller: Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits. DATE 2008: 1378-1381
39	EE	David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller: On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams. ISMVL 2008: 138-143
38	EE	Mitchell A. Thornton, David W. Matula, Laura Spenner, D. Michael Miller: Quantum Logic Implementation of Unary Arithmetic Operations. ISMVL 2008: 202-207
37	EE	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, C. Negrevergne: Quantum Circuit Simplification and Level Compaction. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 436-444 (2008)
2007
36	EE	D. Michael Miller, David Y. Feinstein, Mitchell A. Thornton: Variable Reordering and Sifting for QMDD. ISMVL 2007: 10
35	EE	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Techniques for the synthesis of reversible Toffoli networks. ACM Trans. Design Autom. Electr. Syst. 12(4): (2007)
2006
34	EE	D. Michael Miller, Mitchell A. Thornton: QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits. ISMVL 2006: 30
2005
33	EE	Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck: Quantum Circuit Simplification Using Templates. DATE 2005: 1208-1213
32	EE	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Synthesis of Fredkin-Toffoli reversible networks. IEEE Trans. VLSI Syst. 13(6): 765-769 (2005)
31	EE	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Toffoli network synthesis with templates. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 807-817 (2005)
2004
30		Christine W. Chan, Witold Kinsner, Yingxu Wang, D. Michael Miller: Proceedings of the 3rd IEEE International Conference on Cognitive Informatics (ICCI 2004), 16-17 August 2004, Victoria, Canada IEEE Computer Society 2004
29	EE	D. Michael Miller, Gerhard W. Dueck, Dmitri Maslov: A Synthesis Method for MVL Reversible Logi. ISMVL 2004: 74-80
2003
28	EE	D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck: A transformation based algorithm for reversible logic synthesis. DAC 2003: 318-323
27	EE	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Fredkin/Toffoli Templates for Reversible Logic Synthesis. ICCAD 2003: 256-261
26	EE	D. Michael Miller, Gerhard W. Dueck: On the Size of Multiple-Valued Decision Diagrams. ISMVL 2003: 235-240
25	EE	D. Michael Miller, Rolf Drechsler: Augmented Sifting of Multiple-Valued Decision Diagrams. ISMVL 2003: 375-382
24	EE	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Simplification of Toffoli Networks via Templates. SBCCI 2003: 53-
2002
23	EE	Whitney J. Townsend, Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller: Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations. ACM Great Lakes Symposium on VLSI 2002: 178-183
22	EE	Mitchell A. Thornton, D. Michael Miller, Whitney J. Townsend: Chrestenson Spectrum Computation Using Cayley Color Graphs. ISMVL 2002: 123-129
21	EE	D. Michael Miller, Rolf Drechsler: On the Construction of Multiple-Valued Decision Diagrams. ISMVL 2002: 245-253
20	EE	Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller: Multi-Output Timed Shannon Circuits. ISVLSI 2002: 47-52
2000
19	EE	Elena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio: TOP: An Algorithm for Three-Level Optimization of PLDs. DATE 2000: 751
18	EE	Yasunori Nagata, D. Michael Miller, Masao Mukaidono: Logic Synthesis of Controllers for B-Ternary Asynchronous Systems. ISMVL 2000: 402-
1999
17	EE	Yasunori Nagata, D. Michael Miller, Masao Mukaidono: B-ternary Logic Based Asynchronous Micropipeline. ISMVL 1999: 214-219
1998
16	EE	Yasunori Nagata, D. Michael Miller, Masao Mukaidono: Minimal Test Set Generation for Fault Diagnosis in R-Valued PLAs. ISMVL 1998: 38-
15	EE	D. Michael Miller: An improved method for computing a generalized spectral coefficient. IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 233-238 (1998)
1996
14	EE	D. Michael Miller, Noriaki Muranaka: Multiple-Valued Decision Diagrams with Symmetric Variable Nodes. ISMVL 1996: 242-247
13	EE	Noriaki Muranaka, Shigenobu Arai, Shigeru Imanishi, D. Michael Miller: A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs. ISMVL 1996: 92-97
12	EE	Shujian Zhang, D. Michael Miller, Jon C. Muzio: Notes on "Complexity of the lookup-table minimization problem for FPGA technology mapping". IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1588-1590 (1996)
1995
11	EE	Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller: Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults. J. Electronic Testing 7(3): 209-221 (1995)
1994
10		Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller: Why Cellular Automata are better than LFSRs as Built-in Self-test Generators for Sequential-type Faults. ISCAS 1994: 69-72
9		D. Michael Miller: Spectral Transformation of Multiple-Valued Decision Diagrams. ISMVL 1994: 89-96
1993
8		D. Michael Miller: Multiple-Valued Logic Design Tools. ISMVL 1993: 2-11
7		Noriaki Muranaka, Shigeru Imanishi, D. Michael Miller: Decimal Addition and Subtraction Units Using the p-Valued Decimal Signed-Digit Number Representation. ISMVL 1993: 228-233
1992
6		Shujian Zhang, Rod Byrne, D. Michael Miller: BIST Generators for Sequential Faults. ICCD 1992: 260-263
5		R. Tomczuk, D. Michael Miller: Autocorrelation Techniques for Multi-Bit Decoder PLAs. ISMVL 1992: 355-364
1990
4		Gerhard W. Dueck, D. Michael Miller: RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. ISMVL 1990: 136-143
3	EE	Micaela Serra, Terry Slater, Jon C. Muzio, D. Michael Miller: The analysis of one-dimensional linear cellular automata and their aliasing properties. IEEE Trans. on CAD of Integrated Circuits and Systems 9(7): 767-778 (1990)
1984
2		D. Michael Miller, Jon C. Muzio: Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks. IEEE Trans. Computers 33(8): 765-769 (1984)
1983
1		D. Michael Miller, Jon C. Muzio: Spectral Fault Signatures for Internally Unate Combinational Networks. IEEE Trans. Computers 32(11): 1058-1062 (1983)

Coauthor Index

1	Shigenobu Arai	[13]
2	Rod Byrne	[6] [10] [11]
3	Christine W. Chan	[30]
4	Rolf Drechsler	[20] [21] [23] [25]
5	Elena Dubrova	[19]
6	Gerhard W. Dueck	[4] [24] [26] [27] [28] [29] [31] [32] [33] [35] [37]
7	Peeter Ellervee	[19]
8	David Y. Feinstein	[36] [39] [40]
9	Shigeru Imanishi	[7] [13]
10	Witold Kinsner	[30]
11	Dmitri Maslov	[24] [27] [28] [29] [31] [32] [33] [35] [37]
12	David W. Matula	[38]
13	Masao Mukaidono	[16] [17] [18]
14	Noriaki Muranaka	[7] [13] [14]
15	Jon C. Muzio	[1] [2] [3] [10] [11] [12] [19]
16	Yasunori Nagata	[16] [17] [18]
17	C. Negrevergne	[37]
18	Micaela Serra	[3]
19	Terry Slater	[3]
20	Laura Spenner	[38]
21	Mitchell A. Thornton (Mitchell Aaron Thornton)	[20] [22] [23] [34] [36] [38] [39] [40]
22	R. Tomczuk	[5]
23	Whitney J. Townsend	[22] [23]
24	Yingxu Wang	[30]
25	Christina Young	[33]
26	Shujian Zhang	[6] [10] [11] [12]

Colors in the list of coauthors