2008 |
9 | EE | Rolf Drechsler,
Stephan Eggersglüß,
Görschwin Fey,
Andreas Glowatz,
Friedrich Hapke,
Jürgen Schlöffel,
Daniel Tille:
On Acceleration of SAT-Based ATPG for Industrial Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1329-1333 (2008) |
2007 |
8 | EE | Stephan Eggersglüß,
Daniel Tille,
Görschwin Fey,
Rolf Drechsler,
Andreas Glowatz,
Friedrich Hapke,
Jürgen Schlöffel:
Experimental Studies on SAT-Based ATPG for Gate Delay Faults.
ISMVL 2007: 6 |
7 | EE | Stephan Eggersglüß,
Görschwin Fey,
Rolf Drechsler,
Andreas Glowatz,
Friedrich Hapke,
Jürgen Schlöffel:
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults.
MEMOCODE 2007: 181-187 |
2006 |
6 | EE | Harald P. E. Vranken,
Sandeep Kumar Goel,
Andreas Glowatz,
Jürgen Schlöffel,
Friedrich Hapke:
Fault detection and diagnosis with parity trees for space compaction of test responses.
DAC 2006: 1095-1098 |
5 | EE | Yuyi Tang,
Hans-Joachim Wunderlich,
Piet Engelke,
Ilia Polian,
Bernd Becker,
Jürgen Schlöffel,
Friedrich Hapke,
Michael Wittke:
X-masking during logic BIST and its impact on defect coverage.
IEEE Trans. VLSI Syst. 14(2): 193-202 (2006) |
2005 |
4 | EE | Junhao Shi,
Görschwin Fey,
Rolf Drechsler,
Andreas Glowatz,
Friedrich Hapke,
Jürgen Schlöffel:
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits.
ISVLSI 2005: 212-217 |
2004 |
3 | EE | Yuyi Tang,
Hans-Joachim Wunderlich,
Harald P. E. Vranken,
Friedrich Hapke,
Michael Wittke,
Piet Engelke,
Ilia Polian,
Bernd Becker:
X-Masking During Logic BIST and Its Impact on Defect Coverage.
ITC 2004: 442-451 |
2 | EE | Valentin Gherman,
Hans-Joachim Wunderlich,
Harald P. E. Vranken,
Friedrich Hapke,
Michael Wittke,
Michael Garbers:
Efficient Pattern Mapping for Deterministic Logic BIST.
ITC 2004: 48-56 |
2003 |
1 | EE | Harald P. E. Vranken,
Friedrich Hapke,
Soenke Rogge,
Domenico Chindamo,
Erik H. Volkerink:
ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume.
ITC 2003: 1069-1078 |