| 2009 |
|---|
| 152 | EE | Costas Argyrides,
Ahmad A. Al-Yamani,
Carlos Arthur Lang Lisbôa,
Luigi Carro,
Dhiraj K. Pradhan:
Increasing memory yield in future technologies through innovative design.
ISQED 2009: 622-626 |
| 151 | EE | Jawar Singh,
Jimson Mathew,
Saraju P. Mohanty,
Dhiraj K. Pradhan:
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems.
VLSI Design 2009: 307-312 |
| 2008 |
|---|
| 150 | EE | Mohammad Hosseinabady,
Mohammad Reza Kakoee,
Jimson Mathew,
Dhiraj K. Pradhan:
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs.
DATE 2008: 1370-1373 |
| 149 | EE | Jimson Mathew,
Jawar Singh,
Abusaleh M. Jabir,
Mohammad Hosseinabady,
Dhiraj K. Pradhan:
Fault tolerant bit parallel finite field multipliers using LDPC codes.
ISCAS 2008: 1684-1687 |
| 148 | EE | Jawar Singh,
Jimson Mathew,
Saraju P. Mohanty,
Dhiraj K. Pradhan:
A nano-CMOS process variation induced read failure tolerant SRAM cell.
ISCAS 2008: 3334-3337 |
| 147 | EE | Costas Argyrides,
Stephania Loizidou,
Dhiraj K. Pradhan:
Area Reliability Trade-Off in Improved Reed Muller Coding.
SAMOS 2008: 116-125 |
| 146 | EE | Yi Xin Su,
Jimson Mathew,
Jawar Singh,
Dhiraj K. Pradhan:
Pseudo parallel architecture for AES with error correction.
SoCC 2008: 187-190 |
| 145 | EE | Jawar Singh,
Jimson Mathew,
Dhiraj K. Pradhan,
Saraju P. Mohanty:
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies.
SoCC 2008: 243-246 |
| 144 | EE | Jawar Singh,
Jimson Mathew,
Dhiraj K. Pradhan,
Saraju P. Mohanty:
Failure analysis for ultra low power nano-CMOS SRAM under process variations.
SoCC 2008: 251-254 |
| 143 | EE | Donny Cheung,
Dmitri Maslov,
Jimson Mathew,
Dhiraj K. Pradhan:
On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography.
TQC 2008: 96-104 |
| 142 | EE | Jimson Mathew,
Costas Argyrides,
Abusaleh M. Jabir,
Hafizur Rahaman,
Dhiraj K. Pradhan:
Single Error Correcting Finite Field Multipliers Over GF(2m).
VLSI Design 2008: 33-38 |
| 141 | EE | Jimson Mathew,
Hafizur Rahaman,
Babita R. Jose,
Dhiraj K. Pradhan:
Design of Reversible Finite Field Arithmetic Circuits with Error Detection.
VLSI Design 2008: 453-459 |
| 140 | EE | Jimson Mathew,
Hafizur Rahaman,
A. K. Singh,
Abusaleh M. Jabir,
Dhiraj K. Pradhan:
A Galois Field Based Logic Synthesis Approach with Testability.
VLSI Design 2008: 629-634 |
| 139 | EE | Carlos Arthur Lang Lisbôa,
Costas Argyrides,
Dhiraj K. Pradhan,
Luigi Carro:
Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms.
VTS 2008: 363-370 |
| 138 | EE | Hafizur Rahaman,
Jimson Mathew,
Dhiraj K. Pradhan,
Abusaleh M. Jabir:
C-testable bit parallel multipliers over GF(2m).
ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
| 137 | EE | Hafizur Rahaman,
Jimson Mathew,
Dhiraj K. Pradhan,
Abusaleh M. Jabir:
Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m).
IEEE Trans. Computers 57(9): 1289-1294 (2008) |
| 136 | EE | Abusaleh M. Jabir,
Dhiraj K. Pradhan,
Jimson Mathew:
GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 698-711 (2008) |
| 135 | EE | Jayawant Kakade,
Dimitrios Kagaris,
Dhiraj K. Pradhan:
Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1689-1692 (2008) |
| 2007 |
|---|
| 134 | EE | Costas Argyrides,
Hamid R. Zarandi,
Dhiraj K. Pradhan:
Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories.
DFT 2007: 340-348 |
| 133 | EE | Jawar Singh,
Jimson Mathew,
Mohammad Hosseinabady,
Dhiraj K. Pradhan:
Single Event Upset Detection and Correction.
ICIT 2007: 13-18 |
| 132 | EE | Costas Argyrides,
Dhiraj K. Pradhan:
Highly Reliable Power Aware Memory Design.
IOLTS 2007: 189-190 |
| 131 | EE | Jimson Mathew,
Hafizur Rahaman,
Dhiraj K. Pradhan:
Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set.
IOLTS 2007: 207-208 |
| 130 | EE | Hamid R. Zarandi,
Seyed Ghassem Miremadi,
Costas Argyrides,
Dhiraj K. Pradhan:
Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs.
IPDPS 2007: 1-6 |
| 129 | EE | Hamid R. Zarandi,
Seyed Ghassem Miremadi,
Dhiraj K. Pradhan,
Jimson Mathew:
Soft Error Mitigation in Switch Modules of SRAM-based FPGAs.
ISCAS 2007: 141-144 |
| 128 | EE | R. Stapenhurst,
K. Maharatna,
Jimson Mathew,
José L. Núñez-Yáñez,
Dhiraj K. Pradhan:
On the Hardware Reduction of z-Datapath of Vectoring CORDIC.
ISCAS 2007: 3002-3005 |
| 127 | EE | Costas Argyrides,
Hamid R. Zarandi,
Dhiraj K. Pradhan:
Multiple Upsets Tolerance in SRAM Memory.
ISCAS 2007: 365-368 |
| 126 | EE | Hamid R. Zarandi,
Seyed Ghassem Miremadi,
Dhiraj K. Pradhan,
Jimson Mathew:
CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs.
ISCAS 2007: 3675-3678 |
| 125 | EE | Hamid R. Zarandi,
Seyed Ghassem Miremadi,
Costas Argyrides,
Dhiraj K. Pradhan:
CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs.
ISCAS 2007: 3696-3699 |
| 124 | EE | Hamid R. Zarandi,
Seyed Ghassem Miremadi,
Dhiraj K. Pradhan,
Jimson Mathew:
SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs.
ISQED 2007: 380-385 |
| 123 | EE | S. Ramsundar,
Ahmad A. Al-Yamani,
Dhiraj K. Pradhan:
Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm.
ISQED 2007: 807-813 |
| 122 | EE | Costas Argyrides,
Carlos Arthur Lang Lisbôa,
Luigi Carro,
Dhiraj K. Pradhan:
A soft error robust and power aware memory design.
SBCCI 2007: 300-305 |
| 121 | EE | Hafizur Rahaman,
Jimson Mathew,
Dhiraj K. Pradhan:
Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m).
VLSI Design 2007: 479-484 |
| 120 | EE | Hafizur Rahaman,
Jimson Mathew,
Biplab K. Sikdar,
Dhiraj K. Pradhan:
Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}).
VTS 2007: 422-430 |
| 119 | EE | Abusaleh M. Jabir,
Dhiraj K. Pradhan:
A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields.
IEEE Trans. Computers 56(8): 1119-1132 (2007) |
| 118 | EE | Abusaleh M. Jabir,
Dhiraj K. Pradhan,
T. L. Rajaprabhu,
A. K. Singh:
A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation.
IEEE Trans. Computers 56(8): 1133-1145 (2007) |
| 2006 |
|---|
| 117 | EE | Chunsheng Liu,
Zach Link,
Dhiraj K. Pradhan:
Reuse-based test access and integrated test scheduling for network-on-chip.
DATE 2006: 303-308 |
| 116 | EE | Abusaleh M. Jabir,
Dhiraj K. Pradhan,
Jimson Mathew:
An efficient technique for synthesis and optimization of polynomials in GF(2m).
ICCAD 2006: 151-157 |
| 115 | EE | Chunsheng Liu,
Vikram Iyengar,
Dhiraj K. Pradhan:
Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking.
VTS 2006: 46-51 |
| 2005 |
|---|
| 114 | EE | Dhiraj K. Pradhan,
Dimitri Kagaris,
Rohit Gambhir:
A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage.
IOLTS 2005: 221-226 |
| 113 | EE | Dhiraj K. Pradhan,
Magdy S. Abadir,
Mauricio Varea:
Recent Advances in Verification, Equivalence Checking and SAT-Solvers.
VLSI Design 2005: 14 |
| 112 | EE | Dhiraj K. Pradhan,
Chunsheng Liu:
EBIST: a novel test generator with built-in fault detection capability.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1457-1466 (2005) |
| 2004 |
|---|
| 111 | EE | Subhasis Bhattacharjee,
Dhiraj K. Pradhan:
LPRAM: a low power DRAM with testability.
ASP-DAC 2004: 390-393 |
| 110 | EE | Abusaleh M. Jabir,
Dhiraj K. Pradhan:
MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions.
DATE 2004: 1388-1389 |
| 109 | EE | Chunsheng Liu,
Hamid Sharif,
Érika F. Cota,
Dhiraj K. Pradhan:
Test Scheduling for Network-on-Chip with BIST and Precedence Constraints.
ITC 2004: 1369-1378 |
| 108 | EE | Sathiamoorthy Subbarayan,
Dhiraj K. Pradhan:
NiVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT instances.
SAT 2004 |
| 107 | EE | Sathiamoorthy Subbarayan,
Dhiraj K. Pradhan:
NiVER: Non-increasing Variable Elimination Resolution for Preprocessing SAT Instances.
SAT (Selected Papers 2004: 276-291 |
| 106 | EE | Subhasis Bhattacharjee,
Dhiraj K. Pradhan:
LPRAM: a novel low-power high-performance RAM design with testability and scalability.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 637-651 (2004) |
| 2003 |
|---|
| 105 | EE | Dhiraj K. Pradhan,
Chunsheng Liu,
Krishnendu Chakrabarty:
EBIST: A Novel Test Generator with Built-In Fault Detection Capability.
DATE 2003: 10224-10229 |
| 104 | EE | Elango Ganesan,
Dhiraj K. Pradhan:
Wormhole routing in de Bruijn networks and hyper-de Bruijn networks.
ISCAS (3) 2003: 870-873 |
| 103 | EE | Mitrajit Chatterjee,
Dhiraj K. Pradhan:
A BIST Pattern Generator Design for Near-Perfect Fault Coverage.
IEEE Trans. Computers 52(12): 1543-1558 (2003) |
| 2001 |
|---|
| 102 | EE | Dhiraj K. Pradhan:
Logic Insertion to Speed-Up Logic Verification: A Recent Development.
IOLTW 2001: 61-64 |
| 101 | EE | Magdy S. Abadir,
Scott Davidson,
Vijay Nagasamy,
Dhiraj K. Pradhan,
Prab Varma:
ATPG for Design Errors-Is It Possible?
VTS 2001: 283-285 |
| 2000 |
|---|
| 100 | EE | Mitrajit Chatterjee,
Savita Banerjee,
Dhiraj K. Pradhan:
Buffer Assignment Algorithms on Data Driven ASICs.
IEEE Trans. Computers 49(1): 16-32 (2000) |
| 99 | EE | Debjyoti Paul,
Mitrajit Chatterjee,
Dhiraj K. Pradhan:
VERILAT: verification using logic augmentation and transformations.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1041-1051 (2000) |
| 1999 |
|---|
| 98 | EE | Dhiraj K. Pradhan,
Mitrajit Chatterjee:
GLFSR-a new test pattern generator for built-in-self-test.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 238-247 (1999) |
| 1998 |
|---|
| 97 | EE | Debendra Das Sharma,
Dhiraj K. Pradhan:
Job Scheduling in Mesh Multicomputers.
IEEE Trans. Parallel Distrib. Syst. 9(1): 57-70 (1998) |
| 96 | EE | Mitrajit Chatterjee,
Dhiraj K. Pradhan,
Wolfgang Kunz:
LOT: Logic Optimization with Testability. New transformations for logic synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 386-399 (1998) |
| 1997 |
|---|
| 95 | | Bikram S. Bakshi,
P. Krishna,
Nitin H. Vaidya,
Dhiraj K. Pradhan:
Improving Performance of TCP over Wireless Networks.
ICDCS 1997: 0- |
| 94 | | Dhiraj K. Pradhan,
Nitin H. Vaidya:
Roll-Forward and Rollback Recovery: Performance-Reliability Trade-Off.
IEEE Trans. Computers 46(3): 372-378 (1997) |
| 1996 |
|---|
| 93 | | Dhiraj K. Pradhan,
P. Krishna,
Nitin H. Vaidya:
Recoverable Mobile Environment: Design and Trade-Off Analysis.
FTCS 1996: 16-25 |
| 92 | EE | Wanlin Cao,
Dhiraj K. Pradhan:
Sequential redundancy identification using recursive learning.
ICCAD 1996: 56-62 |
| 91 | EE | Dhiraj K. Pradhan,
Debjyoti Paul,
Mitrajit Chatterjee:
VERILAT: verification using logic augmentation and transformations.
ICCAD 1996: 88-95 |
| 90 | EE | Dhiraj K. Pradhan,
Mitrajit Chatterjee,
Madhu V. Swarna,
Wolfgang Kunz:
Gate-level synthesis for low-power using new transformations.
ISLPED 1996: 297-300 |
| 89 | EE | Bikram S. Bakshi,
P. Krishna,
Dhiraj K. Pradhan,
Nitin H. Vaidya:
Providing Seamless Communication in Mobile Wireless Networks.
LCN 1996: 535-543 |
| 88 | EE | P. Krishna,
Nitin H. Vaidya,
Dhiraj K. Pradhan:
Static and adaptive location management in mobile wireless networks.
Computer Communications 19(4): 321-334 (1996) |
| 87 | EE | Shlomi Dolev,
Dhiraj K. Pradhan,
Jennifer L. Welch:
Modified tree structure for location management in mobile environments.
Computer Communications 19(4): 335-345 (1996) |
| 86 | | Sandeep K. Gupta,
Dhiraj K. Pradhan:
Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa.
IEEE Trans. Computers 45(1): 63-73 (1996) |
| 85 | | Nicholas S. Bowen,
Dhiraj K. Pradhan:
The Effect of Program Behavior on Fault Observability.
IEEE Trans. Computers 45(8): 868-880 (1996) |
| 84 | EE | Srimat T. Chakradhar,
Savita Banerjee,
Rabindra K. Roy,
Dhiraj K. Pradhan:
Synthesis of initializable asynchronous circuits.
IEEE Trans. VLSI Syst. 4(2): 254-263 (1996) |
| 83 | EE | Wolfgang Kunz,
Dhiraj K. Pradhan,
Sudhakar M. Reddy:
A novel framework for logic verification in a synthesis environment.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(1): 20-32 (1996) |
| 82 | | Debendra Das Sharma,
Dhiraj K. Pradhan:
Submesh Allocation in Mesh Multicomputers Using Busy-List: A BestFit Approach with Complete Recognition Capability.
J. Parallel Distrib. Comput. 36(2): 106-118 (1996) |
| 1995 |
|---|
| 81 | | Subodh M. Reddy,
Wolfgang Kunz,
Dhiraj K. Pradhan:
Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment.
DAC 1995: 414-419 |
| 80 | EE | Mitrajit Chatterjee,
Dhiraj K. Pradhan,
Wolfgang Kunz:
LOT: logic optimization with testability-new transformations using recursive learning.
ICCAD 1995: 318-325 |
| 79 | | Shlomi Dolev,
Dhiraj K. Pradhan,
Jennifer L. Welch:
Modified Tree Structure for Location Management in Mobile Environments.
INFOCOM 1995: 530-537 |
| 78 | EE | P. Krishna,
Mainak Chatterjee,
Nitin H. Vaidya,
Dhiraj K. Pradhan:
A Cluster-based Approach for Routing in Ad-Hoc Networks.
Symposium on Mobile and Location-Independent Computing 1995: 1-10 |
| 77 | EE | Mitrajit Chatterjee,
Dhiraj K. Pradhan:
A novel pattern generator for near-perfect fault-coverage.
VTS 1995: 417-425 |
| 76 | | Jeffrey A. Clark,
Dhiraj K. Pradhan:
Fault Injection: A Method for Validating Computer-System Dependability.
IEEE Computer 28(6): 47-56 (1995) |
| 75 | | Nicholas S. Bowen,
Dhiraj K. Pradhan:
A Fault Tolerant Hybrid Memory Structure and Memory Management Algorithms.
IEEE Trans. Computers 44(3): 408-418 (1995) |
| 74 | EE | Debendra Das Sharma,
Dhiraj K. Pradhan:
Processor Allocation in Hypercube Multicomputers: Fast and Efficient Strategies for Cubic and Noncubic Allocation.
IEEE Trans. Parallel Distrib. Syst. 6(10): 1108-1122 (1995) |
| 73 | EE | Dhiraj K. Pradhan,
Jayashree Saxena:
A novel scheme to reduce test application time in circuits with full scan.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1577-1586 (1995) |
| 1994 |
|---|
| 72 | | Savita Banerjee,
Rabindra K. Roy,
Srimat T. Chakradhar,
Dhiraj K. Pradhan:
Signal Transition Graph Transformations for Initializability.
EDAC-ETC-EUROASIC 1994: 670 |
| 71 | | Dhiraj K. Pradhan,
Nitin H. Vaidya:
Roll-Forward and Rollback Recovery: Performance-Reliability Trade-Off.
FTCS 1994: 186-195 |
| 70 | | Savita Banerjee,
Rabindra K. Roy,
Srimat T. Chakradhar,
Dhiraj K. Pradhan:
Initialization Isuues in the Synthesis of Asynchronous Circuits.
ICCD 1994: 447-452 |
| 69 | | Debendra Das Sharma,
G. D. Holland,
Dhiraj K. Pradhan:
Subcube Level Time-Sharing in Hypercube Multicomputers.
ICPP 1994: 134-142 |
| 68 | | P. Krishna,
Nitin H. Vaidya,
Dhiraj K. Pradhan:
Recovery in Multicomputers with Finite Error Detection Latency.
ICPP 1994: 206-210 |
| 67 | | Debendra Das Sharma,
Dhiraj K. Pradhan:
Job Scheduling in Mesh Multicomputers.
ICPP 1994: 251-258 |
| 66 | | Barun K. Kar,
Khadem M. Yusuf,
Dhiraj K. Pradhan:
Bit-Serial Generalized Median Filters.
ISCAS 1994: 85-88 |
| 65 | | Dhiraj K. Pradhan,
Mitrajit Chatterjee:
GLFSR - A New Test Pattern Generator for Built-In Self-Test.
ITC 1994: 481-490 |
| 64 | EE | P. Krishna,
Nitin H. Vaidya,
Dhiraj K. Pradhan:
Location Management in Distributed Mobile Environments.
PDIS 1994: 81-88 |
| 63 | | Srimat T. Chakradhar,
Savita Banerjee,
Rabindra K. Roy,
Dhiraj K. Pradhan:
Synthesis of Initializable Asynchronous Circuits.
VLSI Design 1994: 383-388 |
| 62 | | Dhiraj K. Pradhan,
Nitin H. Vaidya:
Roll-Forward Checkpointing Scheme: A Novel Fault-Tolerant Architecture.
IEEE Trans. Computers 43(10): 1163-1174 (1994) |
| 61 | | Nitin H. Vaidya,
Dhiraj K. Pradhan:
Safe System Level Diagnosis.
IEEE Trans. Computers 43(3): 367-370 (1994) |
| 60 | EE | Wolfgang Kunz,
Dhiraj K. Pradhan:
Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(9): 1143-1158 (1994) |
| 1993 |
|---|
| 59 | | Dhiraj K. Pradhan,
Debendra Das Sharma,
Nitin H. Vaidya:
Roll-Forward Checkpointing Schemes.
Hardware and Software Architectures for Fault Tolerance 1993: 95-116 |
| 58 | EE | Dhiraj K. Pradhan,
Mitrajit Chatterjee,
Savita Banerjee:
Buffer assignment for data driven architectures.
ICCAD 1993: 665-668 |
| 57 | | Jayashree Saxena,
Dhiraj K. Pradhan:
Desgin for Testability of Asynchronous Sequential Circuits.
ICCD 1993: 518-522 |
| 56 | | Nitin H. Vaidya,
Dhiraj K. Pradhan:
Degradable Agreement in the Presence of Byzantine Faults.
ICDCS 1993: 237-244 |
| 55 | | Debendra Das Sharma,
Dhiraj K. Pradhan:
Fast and Efficient Strategies for Cubic and Non-Cubic Allocation in Hypercube Multiprocessors.
ICPP 1993: 118-127 |
| 54 | | Elango Ganesan,
Dhiraj K. Pradhan:
Optimal Broadcasting in Binary de Bruijn Networks and Hyper-de Bruijn Networks.
IPPS 1993: 655-660 |
| 53 | | Jayashree Saxena,
Dhiraj K. Pradhan:
A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits.
ITC 1993: 724-733 |
| 52 | | Debendra Das Sharma,
Dhiraj K. Pradhan:
A Fast and Efficient Strategy for Submesh Allocation in Mesh-Connected Parallel Computers.
SPDP 1993: 682-689 |
| 51 | | Barun K. Kar,
Dhiraj K. Pradhan:
Scalability of Binary deBruijn Networks.
SPDP 1993: 796-799 |
| 50 | | Nicholas S. Bowen,
Dhiraj K. Pradhan:
Processor- and Memory-Based Checkpoint and Rollback Recovery.
IEEE Computer 26(2): 22-31 (1993) |
| 49 | | Abraham Mendelson,
Dominique Thiébaut,
Dhiraj K. Pradhan:
Modeling Live and Dead Lines in Cache Memory Systems.
IEEE Trans. Computers 42(1): 1-14 (1993) |
| 48 | | Nitin H. Vaidya,
Dhiraj K. Pradhan:
Fault-Tolerant Design Strategies for High Reliability and Safety.
IEEE Trans. Computers 42(10): 1195-1206 (1993) |
| 47 | EE | Elango Ganesan,
Dhiraj K. Pradhan:
The Hyper-deBruijn Networks: Scalable Versatile Architecture.
IEEE Trans. Parallel Distrib. Syst. 4(9): 962-978 (1993) |
| 46 | EE | D. D. Sharma,
Fred J. Meyer,
Dhiraj K. Pradhan:
Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model.
IEEE Trans. VLSI Syst. 1(4): 546-558 (1993) |
| 45 | EE | Wolfgang Kunz,
Dhiraj K. Pradhan:
Accelerated dynamic learning for test pattern generation in combinational circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 684-694 (1993) |
| 1992 |
|---|
| 44 | | Yeong-Chang Maa,
Dhiraj K. Pradhan,
Dominique Thiébaut:
A Hierarchical Directory Scheme for Large-Scale Cache-Coherent Multipmcessors.
IPPS 1992: 43-46 |
| 43 | | Sandeep K. Gupta,
Dhiraj K. Pradhan:
Can Concurrent Checkers Help BIST?
ITC 1992: 140-150 |
| 42 | | Wolfgang Kunz,
Dhiraj K. Pradhan:
Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits.
ITC 1992: 816-825 |
| 41 | | Debendra Das Sharma,
Dhiraj K. Pradhan:
A Novel Approach for Subcube Allocation in Hypercube Multiprocessors.
SPDP 1992: 336-345 |
| 40 | | Nicholas S. Bowen,
Dhiraj K. Pradhan:
Virtual Checkpoints: Architecture and Performance.
IEEE Trans. Computers 41(5): 516-525 (1992) |
| 39 | | Nitin H. Vaidya,
Dhiraj K. Pradhan:
A new class of bit- and byte-error control codes.
IEEE Transactions on Information Theory 38(5): 1617- (1992) |
| 1991 |
|---|
| 38 | | Nicholas S. Bowen,
Dhiraj K. Pradhan:
Program Fault Tolerance Based on Memory Access Behavior.
FTCS 1991: 426-435 |
| 37 | | Nitin H. Vaidya,
Dhiraj K. Pradhan:
System Level Diagnosis: Combining Detection and Location.
FTCS 1991: 488-495 |
| 36 | EE | Elango Ganesan,
Dhiraj K. Pradhan:
The hyper-deBruijn multiprocessor networks.
ICDCS 1991: 492-499 |
| 35 | | Mark G. Karpovsky,
Sandeep K. Gupta,
Dhiraj K. Pradhan:
Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model.
ITC 1991: 828-839 |
| 34 | EE | Nicholas S. Bowen,
Dhiraj K. Pradhan:
A virtual memory translation mechanism to support checkpoint and rollback recovery.
SC 1991: 890-899 |
| 33 | | Dhiraj K. Pradhan,
Sandeep K. Gupta:
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression.
IEEE Trans. Computers 40(6): 743-763 (1991) |
| 32 | EE | Fred J. Meyer,
Dhiraj K. Pradhan:
Consensus With Dual Failure Modes.
IEEE Trans. Parallel Distrib. Syst. 2(2): 214-222 (1991) |
| 1990 |
|---|
| 31 | | Abraham Mendelson,
Dominique Thiébaut,
Dhiraj K. Pradhan:
Modeling of Live Lines and True Sharing in Multi-Cache Memory Systems.
ICPP (1) 1990: 326-330 |
| 30 | | Eiji Fujiwara,
Dhiraj K. Pradhan:
Error-Control Coding in Computers.
IEEE Computer 23(7): 63-72 (1990) |
| 29 | | Kifung C. Cheung,
Gurindar S. Sohi,
Kewal K. Saluja,
Dhiraj K. Pradhan:
Design and Analysis of a Gracefully Degrading Interleaved Memory System.
IEEE Trans. Computers 39(1): 63-71 (1990) |
| 28 | | Dhiraj K. Pradhan,
Sandeep K. Gupta,
Mark G. Karpovsky:
Aliasing Probability for Multiple Input Signature Analyzer.
IEEE Trans. Computers 39(4): 586-591 (1990) |
| 1989 |
|---|
| 27 | | Fred J. Meyer,
Dhiraj K. Pradhan:
Dynamic Testing Strategy for Distributed Systems.
IEEE Trans. Computers 38(3): 356-365 (1989) |
| 26 | | Fred J. Meyer,
Dhiraj K. Pradhan:
Modeling Defect Spatial Distribution.
IEEE Trans. Computers 38(4): 538-546 (1989) |
| 25 | | Maheswara R. Samatham,
Dhiraj K. Pradhan:
The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI.
IEEE Trans. Computers 38(4): 567-581 (1989) |
| 1988 |
|---|
| 24 | | Dhiraj K. Pradhan,
Nirmala R. Kamath:
RTRAM: Reconfigurable and Testable Multi-Bit RAM Design.
ITC 1988: 263-278 |
| 23 | | Sandeep K. Gupta,
Dhiraj K. Pradhan:
A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability.
ITC 1988: 329-342 |
| 22 | | Najmi T. Jarwala,
Dhiraj K. Pradhan:
TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's.
IEEE Trans. Computers 37(10): 1235-1250 (1988) |
| 21 | | Fred J. Meyer,
Dhiraj K. Pradhan:
Flip-Trees: Fault-Tolerant Graphs with Wide Containers.
IEEE Trans. Computers 37(4): 472-478 (1988) |
| 1987 |
|---|
| 20 | EE | Kifung C. Cheung,
Gurindar S. Sohi,
Kewal K. Saluja,
Dhiraj K. Pradhan:
Organization and Analysis of a Gracefully-Degrading Interleaved Memory System.
ISCA 1987: 224-231 |
| 19 | | Israel Koren,
Dhiraj K. Pradhan:
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems.
IEEE Trans. Computers 36(3): 344-355 (1987) |
| 1985 |
|---|
| 18 | | Maheswara R. Samatham,
Dhiraj K. Pradhan:
The de Bruijn Multiprocessor Network: A Versatile Sorting Network.
ISCA 1985: 360-367 |
| 17 | | Dhiraj K. Pradhan:
Dynamically Restructurable Fault-Tolerant Processor Network Architectures.
IEEE Trans. Computers 34(5): 434-447 (1985) |
| 1983 |
|---|
| 16 | | Dhiraj K. Pradhan:
Sequential Network Design Using Extra Inputs for Fault Detection.
IEEE Trans. Computers 32(3): 319-323 (1983) |
| 1982 |
|---|
| 15 | | Dhiraj K. Pradhan:
On a Class of Fault-Tolerant Multiprocessor Network Architectures.
ICDCS 1982: 302-311 |
| 14 | | Bella Bose,
Dhiraj K. Pradhan:
Optimal Unidirectional Error Detecting/Correcting Codes.
IEEE Trans. Computers 31(6): 564-568 (1982) |
| 13 | | Dhiraj K. Pradhan,
Sudhakar M. Reddy:
A Fault-Tolerant Communication Architecture for Distributed Systems.
IEEE Trans. Computers 31(9): 863-870 (1982) |
| 1981 |
|---|
| 12 | | Kyushik Son,
Dhiraj K. Pradhan:
Completely Self-Checking Checkers in PLAs.
ITC 1981: 231-240 |
| 1980 |
|---|
| 11 | | Kolar L. Kodandapani,
Dhiraj K. Pradhan:
Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets.
IEEE Trans. Computers 29(1): 55-59 (1980) |
| 10 | | Dhiraj K. Pradhan:
A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications.
IEEE Trans. Computers 29(6): 471-481 (1980) |
| 9 | | Dhiraj K. Pradhan,
Kolar L. Kodandapani:
A Uniform Representation of Single- and Multistage Interconnection Networks Used in SIMD Machines.
IEEE Trans. Computers 29(9): 777-791 (1980) |
| 1978 |
|---|
| 8 | | Dhiraj K. Pradhan:
Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays.
IEEE Trans. Computers 27(2): 181-187 (1978) |
| 7 | | Dhiraj K. Pradhan:
A Theory of Galois Switching Functions.
IEEE Trans. Computers 27(3): 239-248 (1978) |
| 6 | | Dhiraj K. Pradhan:
Asynchronous State Assignments with Unateness Properties and Fault-Secure Design.
IEEE Trans. Computers 27(5): 396-404 (1978) |
| 5 | | Dhiraj K. Pradhan:
Fault-Tolerant Asynchronous Networks Using Read-Only Memories.
IEEE Trans. Computers 27(7): 674-679 (1978) |
| 1977 |
|---|
| 4 | | M. Y. Hsiao,
Arvind M. Patel,
Dhiraj K. Pradhan:
Store Address Generator with On-Line Fault-Detection Capability.
IEEE Trans. Computers 26(11): 1144-1151 (1977) |
| 3 | EE | L. C. Chang,
Dhiraj K. Pradhan:
A graph-structural approach for the generalization of data management systems.
Inf. Sci. 12(1): 1-18 (1977) |
| 1976 |
|---|
| 2 | | Dhiraj K. Pradhan,
Sudhakar M. Reddy:
Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes.
IEEE Trans. Computers 25(9): 945-949 (1976) |
| 1975 |
|---|
| 1 | | Dhiraj K. Pradhan,
Arvind M. Patel:
Reed-Muller Like Canonic Forms for Multivalued Functions.
IEEE Trans. Computers 24(2): 206-210 (1975) |
