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Ting-Chi Wang

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2008
34EEJhih-Rong Gao, Pei-Ci Wu, Ting-Chi Wang: A new global router for modern designs. ASP-DAC 2008: 232-237
33EEMing-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang: An MILP-based wire spreading algorithm for PSM-aware layout modification. ASP-DAC 2008: 364-369
32EETien-Yuan Hsu, Ting-Chi Wang: A generalized network flow based algorithm for power-aware FPGA memory mapping. DAC 2008: 30-33
31EEYen-Jung Chang, Yu-Ting Lee, Ting-Chi Wang: NTHU-Route 2.0: a fast and stable global router. ICCAD 2008: 338-343
30EEKuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao: Optimal post-routing redundant via insertion. ISPD 2008: 111-117
29EEKuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao: Fast and Optimal Redundant Via Insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2197-2208 (2008)
2007
28EEChung-Wei Lin, Ming-Chao Tsai, Kuang-Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang: Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. ASP-DAC 2007: 238-243
27EEPei-Ci Wu, Jhih-Rong Gao, Ting-Chi Wang: A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction. ASP-DAC 2007: 262-267
26EETien-Ting Fang, Ting-Chi Wang: Fast Buffered Delay Estimation Considering Process Variations. ASP-DAC 2007: 702-707
2006
25EEKuang-Yao Lee, Ting-Chi Wang: Post-routing redundant via insertion for yield/reliability improvement. ASP-DAC 2006: 303-308
24EEKuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao: Post-routing redundant via insertion and line end extension with via density consideration. ICCAD 2006: 633-640
2005
23EEZhong-Ching Lu, Ting-Chi Wang: Concurrent flip-flop and buffer insertion with adaptive blockage avoidance. ASP-DAC 2005: 19-22
22EEYun-Ru Wu, Ming-Chao Tsai, Ting-Chi Wang: Maze routing with OPC consideration. ASP-DAC 2005: 198-203
21EEHao-Yueh Hsieh, Ting-Chi Wang: Simple yet effective algorithms for block and I/O buffer placement in flip-chip design. ISCAS (2) 2005: 1879-1882
2004
20EECliff C. N. Sze, Ting-Chi Wang, Li-C. Wang: Multilevel circuit clustering for delay minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1073-1085 (2004)
2003
19EECliff C. N. Sze, Ting-Chi Wang: Optimal circuit clustering for delay minimization under a more general delay model. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 646-651 (2003)
2002
18EES. Dhamdhere, Ningyu Zhou, Ting-Chi Wang: Module placement with pre-placed modules using the corner block list representation. ISCAS (1) 2002: 349-352
17EECliff C. N. Sze, Ting-Chi Wang: Optimal circuit clustering with variable interconnect delay. ISCAS (4) 2002: 707-710
16 Cliff C. N. Sze, Ting-Chi Wang: Multi-Level Circuit Clustering for Delay Minimization. IWLS 2002: 227-232
2001
15EEJianbang Lai, Ming-Shiun Lin, Ting-Chi Wang, Li-C. Wang: Module placement with boundary constraints using the sequence-pair representation. ASP-DAC 2001: 515-520
14EEZhi-Hong Wang, En-Cheng Liu, Jianbang Lai, Ting-Chi Wang: Power minization in LUT-based FPGA technology mapping. ASP-DAC 2001: 635-640
13EEYi-He Jiang, Jianbang Lai, Ting-Chi Wang: Module placement with pre-placed modules using the B*-tree representation. ISCAS (5) 2001: 347-350
12EEEn-Cheng Liu, Ming-Shiun Lin, Jianbang Lai, Ting-Chi Wang: Slicing floorplan design with boundary-constrained modules. ISPD 2001: 124-129
2000
11EEHsun-Cheng Lee, Ting-Chi Wang: Feasible two-way circuit partitioning with complex resource constraints. ASP-DAC 2000: 435-440
10EEJennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer: On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. Asian Test Symposium 2000: 151-
1999
9EEJan-Yang Chang, Yu-Chen Liu, Ting-Chi Wang: Faster and Better Spectral Algorithms for Multi-Way Partitioning. ASP-DAC 1999: 81-
1997
8EEYachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu: Routing for symmetric FPGAs and FPICs. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 20-31 (1997)
1995
7EETing-Chi Wang, Martin D. F. Wong, Yachyang Sun, Chak-Kuen Wong: Optimal net assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 265-269 (1995)
6EET. W. Her, Ting-Chi Wang, Martin D. F. Wong: Performance-driven channel pin assignment algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 14(7): 849-857 (1995)
1993
5EEYachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu: Routing for symmetric FPGAs and FPICs. ICCAD 1993: 486-490
4 Yao-Ping Chen, Ting-Chi Wang, D. F. Wong: A Graph Partitioning Problem for Multiple-chip Design. ISCAS 1993: 1778-1781
1992
3EETing-Chi Wang, D. F. Wong: A Graph Theoretic Technique to Speed up Floorplan Area Optimization. DAC 1992: 62-68
2EETing-Chi Wang, Martin D. F. Wong: Optimal floorplan area optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 11(8): 992-1002 (1992)
1990
1EETing-Chi Wang, D. F. Wong: An Optimal Algorithm for Floorplan Area Optimization. DAC 1990: 180-186

Coauthor Index

1Jan-Yang Chang [9]
2Yao-Wen Chang [28]
3Yen-Jung Chang [31]
4Kai-Yuan Chao [24] [29] [30]
5Tai-Chen Chen [28]
6Yao-Ping Chen [4]
7Brad Cobb [10]
8S. Dhamdhere [18]
9Jennifer Dworak [10]
10Tien-Ting Fang [26]
11Jhih-Rong Gao [27] [34]
12Michael R. Grimaila [10]
13T. W. Her [6]
14Hao-Yueh Hsieh [21]
15Tien-Yuan Hsu [32]
16Yi-He Jiang [13]
17Cheng-Kok Koh [29] [30]
18Jianbang Lai [12] [13] [14] [15]
19Hsun-Cheng Lee [11]
20Kuang-Yao Lee [24] [25] [28] [29] [30]
21Yu-Ting Lee [31]
22Chung-Wei Lin [28]
23Ming-Shiun Lin [12] [15]
24Yung-Chia Lin [33]
25C. L. Liu (Chung Laung (Dave) Liu) [5] [8]
26En-Cheng Liu [12] [14]
27Yu-Chen Liu [9]
28Zhong-Ching Lu [23]
29M. Ray Mercer [10]
30Yachyang Sun [5] [7] [8]
31Cliff C. N. Sze (Chin Ngai Sze, Cliff N. Sze) [16] [17] [19] [20]
32Ming-Chao Tsai [22] [28] [33]
33Li-C. Wang [10] [15] [20]
34Zhi-Hong Wang [14]
35Chak-Kuen Wong (C. K. Wong) [5] [7] [8]
36Martin D. F. Wong (D. F. Wong) [1] [2] [3] [4] [6] [7]
37Pei-Ci Wu [27] [34]
38Yun-Ru Wu [22]
39Ningyu Zhou [18]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)