| 2008 |
|---|
| 34 | EE | Jhih-Rong Gao,
Pei-Ci Wu,
Ting-Chi Wang:
A new global router for modern designs.
ASP-DAC 2008: 232-237 |
| 33 | EE | Ming-Chao Tsai,
Yung-Chia Lin,
Ting-Chi Wang:
An MILP-based wire spreading algorithm for PSM-aware layout modification.
ASP-DAC 2008: 364-369 |
| 32 | EE | Tien-Yuan Hsu,
Ting-Chi Wang:
A generalized network flow based algorithm for power-aware FPGA memory mapping.
DAC 2008: 30-33 |
| 31 | EE | Yen-Jung Chang,
Yu-Ting Lee,
Ting-Chi Wang:
NTHU-Route 2.0: a fast and stable global router.
ICCAD 2008: 338-343 |
| 30 | EE | Kuang-Yao Lee,
Cheng-Kok Koh,
Ting-Chi Wang,
Kai-Yuan Chao:
Optimal post-routing redundant via insertion.
ISPD 2008: 111-117 |
| 29 | EE | Kuang-Yao Lee,
Cheng-Kok Koh,
Ting-Chi Wang,
Kai-Yuan Chao:
Fast and Optimal Redundant Via Insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2197-2208 (2008) |
| 2007 |
|---|
| 28 | EE | Chung-Wei Lin,
Ming-Chao Tsai,
Kuang-Yao Lee,
Tai-Chen Chen,
Ting-Chi Wang,
Yao-Wen Chang:
Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability.
ASP-DAC 2007: 238-243 |
| 27 | EE | Pei-Ci Wu,
Jhih-Rong Gao,
Ting-Chi Wang:
A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction.
ASP-DAC 2007: 262-267 |
| 26 | EE | Tien-Ting Fang,
Ting-Chi Wang:
Fast Buffered Delay Estimation Considering Process Variations.
ASP-DAC 2007: 702-707 |
| 2006 |
|---|
| 25 | EE | Kuang-Yao Lee,
Ting-Chi Wang:
Post-routing redundant via insertion for yield/reliability improvement.
ASP-DAC 2006: 303-308 |
| 24 | EE | Kuang-Yao Lee,
Ting-Chi Wang,
Kai-Yuan Chao:
Post-routing redundant via insertion and line end extension with via density consideration.
ICCAD 2006: 633-640 |
| 2005 |
|---|
| 23 | EE | Zhong-Ching Lu,
Ting-Chi Wang:
Concurrent flip-flop and buffer insertion with adaptive blockage avoidance.
ASP-DAC 2005: 19-22 |
| 22 | EE | Yun-Ru Wu,
Ming-Chao Tsai,
Ting-Chi Wang:
Maze routing with OPC consideration.
ASP-DAC 2005: 198-203 |
| 21 | EE | Hao-Yueh Hsieh,
Ting-Chi Wang:
Simple yet effective algorithms for block and I/O buffer placement in flip-chip design.
ISCAS (2) 2005: 1879-1882 |
| 2004 |
|---|
| 20 | EE | Cliff C. N. Sze,
Ting-Chi Wang,
Li-C. Wang:
Multilevel circuit clustering for delay minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1073-1085 (2004) |
| 2003 |
|---|
| 19 | EE | Cliff C. N. Sze,
Ting-Chi Wang:
Optimal circuit clustering for delay minimization under a more general delay model.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 646-651 (2003) |
| 2002 |
|---|
| 18 | EE | S. Dhamdhere,
Ningyu Zhou,
Ting-Chi Wang:
Module placement with pre-placed modules using the corner block list representation.
ISCAS (1) 2002: 349-352 |
| 17 | EE | Cliff C. N. Sze,
Ting-Chi Wang:
Optimal circuit clustering with variable interconnect delay.
ISCAS (4) 2002: 707-710 |
| 16 | | Cliff C. N. Sze,
Ting-Chi Wang:
Multi-Level Circuit Clustering for Delay Minimization.
IWLS 2002: 227-232 |
| 2001 |
|---|
| 15 | EE | Jianbang Lai,
Ming-Shiun Lin,
Ting-Chi Wang,
Li-C. Wang:
Module placement with boundary constraints using the sequence-pair representation.
ASP-DAC 2001: 515-520 |
| 14 | EE | Zhi-Hong Wang,
En-Cheng Liu,
Jianbang Lai,
Ting-Chi Wang:
Power minization in LUT-based FPGA technology mapping.
ASP-DAC 2001: 635-640 |
| 13 | EE | Yi-He Jiang,
Jianbang Lai,
Ting-Chi Wang:
Module placement with pre-placed modules using the B*-tree representation.
ISCAS (5) 2001: 347-350 |
| 12 | EE | En-Cheng Liu,
Ming-Shiun Lin,
Jianbang Lai,
Ting-Chi Wang:
Slicing floorplan design with boundary-constrained modules.
ISPD 2001: 124-129 |
| 2000 |
|---|
| 11 | EE | Hsun-Cheng Lee,
Ting-Chi Wang:
Feasible two-way circuit partitioning with complex resource constraints.
ASP-DAC 2000: 435-440 |
| 10 | EE | Jennifer Dworak,
Michael R. Grimaila,
Brad Cobb,
Ting-Chi Wang,
Li-C. Wang,
M. Ray Mercer:
On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction.
Asian Test Symposium 2000: 151- |
| 1999 |
|---|
| 9 | EE | Jan-Yang Chang,
Yu-Chen Liu,
Ting-Chi Wang:
Faster and Better Spectral Algorithms for Multi-Way Partitioning.
ASP-DAC 1999: 81- |
| 1997 |
|---|
| 8 | EE | Yachyang Sun,
Ting-Chi Wang,
Chak-Kuen Wong,
C. L. Liu:
Routing for symmetric FPGAs and FPICs.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 20-31 (1997) |
| 1995 |
|---|
| 7 | EE | Ting-Chi Wang,
Martin D. F. Wong,
Yachyang Sun,
Chak-Kuen Wong:
Optimal net assignment.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 265-269 (1995) |
| 6 | EE | T. W. Her,
Ting-Chi Wang,
Martin D. F. Wong:
Performance-driven channel pin assignment algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(7): 849-857 (1995) |
| 1993 |
|---|
| 5 | EE | Yachyang Sun,
Ting-Chi Wang,
Chak-Kuen Wong,
C. L. Liu:
Routing for symmetric FPGAs and FPICs.
ICCAD 1993: 486-490 |
| 4 | | Yao-Ping Chen,
Ting-Chi Wang,
D. F. Wong:
A Graph Partitioning Problem for Multiple-chip Design.
ISCAS 1993: 1778-1781 |
| 1992 |
|---|
| 3 | EE | Ting-Chi Wang,
D. F. Wong:
A Graph Theoretic Technique to Speed up Floorplan Area Optimization.
DAC 1992: 62-68 |
| 2 | EE | Ting-Chi Wang,
Martin D. F. Wong:
Optimal floorplan area optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(8): 992-1002 (1992) |
| 1990 |
|---|
| 1 | EE | Ting-Chi Wang,
D. F. Wong:
An Optimal Algorithm for Floorplan Area Optimization.
DAC 1990: 180-186 |
