| 2009 |
|---|
| 31 | EE | Sobeeh Almukhaizim,
Ozgur Sinanoglu:
Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 298-302 (2009) |
| 2008 |
|---|
| 30 | EE | Ozgur Sinanoglu,
Erik Jan Marinissen:
Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing.
DATE 2008: 182-187 |
| 29 | EE | Ozgur Sinanoglu:
Scan Architecture With Align-Encode.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2303-2316 (2008) |
| 28 | EE | Ozgur Sinanoglu,
Tsvetomir Petrov:
Isolation Techniques for Soft Cores.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1453-1466 (2008) |
| 27 | EE | Ozgur Sinanoglu:
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations.
J. Electronic Testing 24(4): 335-351 (2008) |
| 26 | EE | Ozgur Sinanoglu:
Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells.
J. Electronic Testing 24(5): 439-448 (2008) |
| 2007 |
|---|
| 25 | EE | Ozgur Sinanoglu,
Tsvetomir Petrov:
A non-intrusive isolation approach for soft cores.
DATE 2007: 27-32 |
| 24 | EE | Ozgur Sinanoglu,
Philip Schremmer:
Diagnosis, modeling and tolerance of scan chain hold-time violations.
DATE 2007: 516-521 |
| 23 | EE | Ozgur Sinanoglu:
Low Cost Scan Test by Test Correlation Utilization.
J. Comput. Sci. Technol. 22(5): 681-694 (2007) |
| 2005 |
|---|
| 22 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Test power reductions through computationally efficient, decoupled scan chain modifications.
IEEE Transactions on Reliability 54(2): 215-223 (2005) |
| 21 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Efficient RT-Level Fault Diagnosis.
J. Comput. Sci. Technol. 20(2): 166-174 (2005) |
| 2004 |
|---|
| 20 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Efficient RT-level fault diagnosis methodology.
ASP-DAC 2004: 212-217 |
| 19 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Scan Power Minimization through Stimulus and Response Transformations.
DATE 2004: 404-409 |
| 18 | EE | Baris Arslan,
Ozgur Sinanoglu,
Alex Orailoglu:
Extending the Applicability of Parallel-Serial Scan Designs.
ICCD 2004: 200-203 |
| 17 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Autonomous Yet Deterministic Test of SOC Cores.
ITC 2004: 1359-1368 |
| 16 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Fast and energy-frugal deterministic test through efficient compression and compaction techniques.
Journal of Systems Architecture 50(5): 257-266 (2004) |
| 2003 |
|---|
| 15 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test.
Asian Test Symposium 2003: 202-209 |
| 14 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Hierarchical Constraint Conscious RT-level Test Generation.
DSD 2003: 312-318 |
| 13 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Partial Core Encryption for Performance-Efficient Test of SOCs.
ICCAD 2003: 91-94 |
| 12 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Aggressive Test Power Reduction Through Test Stimuli Transformation.
ICCD 2003: 542-547 |
| 11 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Modeling Scan Chain Modifications For Scan-in Test Power Minimization.
ITC 2003: 602-611 |
| 10 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Compacting Test Responses for Deeply Embedded SoC Cores.
IEEE Design & Test of Computers 20(4): 22-30 (2003) |
| 9 | EE | Ozgur Sinanoglu,
Ismet Bayraktaroglu,
Alex Orailoglu:
Reducing Average and Peak Test Power Through Scan Chain Modification.
J. Electronic Testing 19(4): 457-467 (2003) |
| 2002 |
|---|
| 8 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation.
DFT 2002: 325-333 |
| 7 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
A novel scan architecture for power-efficient, rapid test.
ICCAD 2002: 299-303 |
| 6 | EE | Ozgur Sinanoglu,
Ismet Bayraktaroglu,
Alex Orailoglu:
Scan Power Reduction Through Test Data Transition Frequency Analysis.
ITC 2002: 844-850 |
| 5 | EE | Ozgur Sinanoglu,
Ismet Bayraktaroglu,
Alex Orailoglu:
Test Power Reduction through Minimization of Scan Chain Transitions.
VTS 2002: 166-172 |
| 4 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Efficient Construction of Aliasing-Free Compaction Circuitry.
IEEE Micro 22(5): 82-92 (2002) |
| 2001 |
|---|
| 3 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
Compaction Schemes with Minimum Test Application Time.
Asian Test Symposium 2001: 199-204 |
| 2 | | Ozgur Sinanoglu,
Alex Orailoglu:
Space and time compaction schemes for embedded cores.
ITC 2001: 521-529 |
| 1 | EE | Ozgur Sinanoglu,
Alex Orailoglu:
RT-level Fault Simulation Based on Symbolic Propagation.
VTS 2001: 240-245 |
