Ozgur Sinanoglu

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

31EESobeeh Almukhaizim, Ozgur Sinanoglu: Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test. IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 298-302 (2009)
30EEOzgur Sinanoglu, Erik Jan Marinissen: Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing. DATE 2008: 182-187
29EEOzgur Sinanoglu: Scan Architecture With Align-Encode. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2303-2316 (2008)
28EEOzgur Sinanoglu, Tsvetomir Petrov: Isolation Techniques for Soft Cores. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1453-1466 (2008)
27EEOzgur Sinanoglu: Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations. J. Electronic Testing 24(4): 335-351 (2008)
26EEOzgur Sinanoglu: Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells. J. Electronic Testing 24(5): 439-448 (2008)
25EEOzgur Sinanoglu, Tsvetomir Petrov: A non-intrusive isolation approach for soft cores. DATE 2007: 27-32
24EEOzgur Sinanoglu, Philip Schremmer: Diagnosis, modeling and tolerance of scan chain hold-time violations. DATE 2007: 516-521
23EEOzgur Sinanoglu: Low Cost Scan Test by Test Correlation Utilization. J. Comput. Sci. Technol. 22(5): 681-694 (2007)
22EEOzgur Sinanoglu, Alex Orailoglu: Test power reductions through computationally efficient, decoupled scan chain modifications. IEEE Transactions on Reliability 54(2): 215-223 (2005)
21EEOzgur Sinanoglu, Alex Orailoglu: Efficient RT-Level Fault Diagnosis. J. Comput. Sci. Technol. 20(2): 166-174 (2005)
20EEOzgur Sinanoglu, Alex Orailoglu: Efficient RT-level fault diagnosis methodology. ASP-DAC 2004: 212-217
19EEOzgur Sinanoglu, Alex Orailoglu: Scan Power Minimization through Stimulus and Response Transformations. DATE 2004: 404-409
18EEBaris Arslan, Ozgur Sinanoglu, Alex Orailoglu: Extending the Applicability of Parallel-Serial Scan Designs. ICCD 2004: 200-203
17EEOzgur Sinanoglu, Alex Orailoglu: Autonomous Yet Deterministic Test of SOC Cores. ITC 2004: 1359-1368
16EEOzgur Sinanoglu, Alex Orailoglu: Fast and energy-frugal deterministic test through efficient compression and compaction techniques. Journal of Systems Architecture 50(5): 257-266 (2004)
15EEOzgur Sinanoglu, Alex Orailoglu: Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test. Asian Test Symposium 2003: 202-209
14EEOzgur Sinanoglu, Alex Orailoglu: Hierarchical Constraint Conscious RT-level Test Generation. DSD 2003: 312-318
13EEOzgur Sinanoglu, Alex Orailoglu: Partial Core Encryption for Performance-Efficient Test of SOCs. ICCAD 2003: 91-94
12EEOzgur Sinanoglu, Alex Orailoglu: Aggressive Test Power Reduction Through Test Stimuli Transformation. ICCD 2003: 542-547
11EEOzgur Sinanoglu, Alex Orailoglu: Modeling Scan Chain Modifications For Scan-in Test Power Minimization. ITC 2003: 602-611
10EEOzgur Sinanoglu, Alex Orailoglu: Compacting Test Responses for Deeply Embedded SoC Cores. IEEE Design & Test of Computers 20(4): 22-30 (2003)
9EEOzgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu: Reducing Average and Peak Test Power Through Scan Chain Modification. J. Electronic Testing 19(4): 457-467 (2003)
8EEOzgur Sinanoglu, Alex Orailoglu: Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation. DFT 2002: 325-333
7EEOzgur Sinanoglu, Alex Orailoglu: A novel scan architecture for power-efficient, rapid test. ICCAD 2002: 299-303
6EEOzgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu: Scan Power Reduction Through Test Data Transition Frequency Analysis. ITC 2002: 844-850
5EEOzgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu: Test Power Reduction through Minimization of Scan Chain Transitions. VTS 2002: 166-172
4EEOzgur Sinanoglu, Alex Orailoglu: Efficient Construction of Aliasing-Free Compaction Circuitry. IEEE Micro 22(5): 82-92 (2002)
3EEOzgur Sinanoglu, Alex Orailoglu: Compaction Schemes with Minimum Test Application Time. Asian Test Symposium 2001: 199-204
2 Ozgur Sinanoglu, Alex Orailoglu: Space and time compaction schemes for embedded cores. ITC 2001: 521-529
1EEOzgur Sinanoglu, Alex Orailoglu: RT-level Fault Simulation Based on Symbolic Propagation. VTS 2001: 240-245

Coauthor Index

1Sobeeh Almukhaizim [31]
2Baris Arslan [18]
3Ismet Bayraktaroglu [5] [6] [9]
4Erik Jan Marinissen [30]
5Alex Orailoglu [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22]
6Tsvetomir Petrov [25] [28]
7Philip Schremmer [24]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)