Sarvesh H. Kulkarni

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8EESarvesh H. Kulkarni, D. M. Sylvester, David T. Blaauw: Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 481-494 (2008)
7EESarvesh H. Kulkarni, Dennis Sylvester: Power distribution techniques for dual VDD circuits. ASP-DAC 2006: 838-843
6EESarvesh H. Kulkarni, Dennis Sylvester, David Blaauw: A statistical framework for post-silicon tuning through body bias clustering. ICCAD 2006: 39-46
5EESarvesh H. Kulkarni, Dennis Sylvester: Power Distribution Techniques for Dual VDD Circuits. J. Low Power Electronics 2(2): 217-229 (2006)
4EESarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester: A new algorithm for improved VDD assignment in low power dual VDD systems. ISLPED 2004: 200-205
3EESarvesh H. Kulkarni, Dennis Sylvester: High performance level conversion for dual VDD design. IEEE Trans. VLSI Syst. 12(9): 926-936 (2004)
2EERuchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni: Pushing ASIC performance in a power envelope. DAC 2003: 788-793
1EERobert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David Blaauw: An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages. ISVLSI 2003: 149-154

Coauthor Index

1Robert Bai [1]
2David Blaauw (David T. Blaauw) [1] [6] [8]
3John M. Cohn [2]
4David S. Kung [2]
5Wesley Kwong [1]
6David Z. Pan (David Zhigang Pan) [2]
7Ruchir Puri [2]
8Ashish Srivastava [1] [2] [4]
9Leon Stok [2]
10D. M. Sylvester [8]
11Dennis Sylvester [1] [2] [3] [4] [5] [6] [7]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)