DATE 2002:
Paris,
France
2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France.
IEEE Computer Society 2002, ISBN 0-7695-1471-5 BibTeX
@proceedings{DBLP:conf/date/2002,
title = {2002 Design, Automation and Test in Europe Conference and Exposition
(DATE 2002), 4-8 March 2002, Paris, France},
booktitle = {DATE},
publisher = {IEEE Computer Society},
year = {2002},
isbn = {0-7695-1471-5},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Plenary - Keynote Session
How to Choose Semiconductor IP?
Formal Verification of Complex Designs
Cooling Layout Arrangements
Defect Oriented Test
Power Analysis and Management in Networks and Processors
Panel - What is the Right IP Business Model?
SAT and BDD Techniques
Technology and Interconnect Issues in Low Power Design
- Luca Macchiarulo, Enrico Macii, Massimo Poncino:
Wire Placement for Crosstalk Energy Minimization in Address Buses.
158-162
Electronic Edition (link) BibTeX
- Chris H. Kim, Kaushik Roy:
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction.
163-167
Electronic Edition (link) BibTeX
- Ana Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau:
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints.
168-175
Electronic Edition (link) BibTeX
- Arindam Mukherjee, Kai Wang, Lauren Hui Chen, Malgorzata Marek-Sadowska:
Sizing Power/Ground Meshes for Clocking and Computing Circuit Components.
176-185
Electronic Edition (link) BibTeX
Advanced Mixed Signal Test
- Ramakrishna Voorakaranam, Sasikumar Cherubal, Abhijit Chatterjee:
A Signature Test Framework for Rapid Production Testing of RF Circuits.
186-191
Electronic Edition (link) BibTeX
- Carlo Guardiani, Patrick McNamara, Lidia Daldoss, Sharad Saxena, Stefano Zanella, Wei Xiang, Suli Liu:
Analog IP Testing: Diagnosis and Optimization.
192-196
Electronic Edition (link) BibTeX
- Christoph Hoffmann:
A New Design Flow and Testability Measure for the Generation of a Structural Test and BIST for Analogue and Mixed-Signal Circuits.
197-204
Electronic Edition (link) BibTeX
- Y. Lechuga, R. Mozuelos, Mar Martínez, Salvador Bracho:
Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal Ics.
205-213
Electronic Edition (link) BibTeX
Collaborative Design
- L. Ghanmi, A. Ghrab, M. Hamdoun, B. Missaoui, K. Skiba, Gabriele Saucier:
E-Design Based on the Reuse Paradigm.
214-220
Electronic Edition (link) BibTeX
- André Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová:
Internet-Based Collaborative Test Generation with MOSCITO.
221-226
Electronic Edition (link) BibTeX
- Tom J. Kazmierski, Neil Clayton:
A Two-Tier Distributed Electronic Design Framework.
227-231
Electronic Edition (link) BibTeX
- Achim Rettberg, Wolfgang Thronicke:
Embedded System Design Based On Webservices.
232-237
Electronic Edition (link) BibTeX
Panel - Who Owns the Platform?
Embedded Tutorial - The Need for Infrastructure IP in SoCs
Advances in Logic Synthesis
Novel Applications of Symbolic Techniques to Analogue and Digital Circuit Design
- Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics.
268-273
Electronic Edition (link) BibTeX
- Rolf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke:
Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits.
274-278
Electronic Edition (link) BibTeX
- Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices.
279-284
Electronic Edition (link) BibTeX
- Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre:
Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification.
285-291
Electronic Edition (link) BibTeX
EDA Tools for RF:
Myth or Reality?
Platform-Based Design and Virtual-Component Reuse
Analogue Circuit Characterisation and Simulation
Panel - MEDEA+ and ITRS Roadmaps
Asynchronous Circuits and Clock Scheduling
Analogue and Mixed-Signal Systems
- Michaël Goffioul, Piet Wambacq, Gerd Vandersteen, Stéphane Donnay:
Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach .
352-356
Electronic Edition (link) BibTeX
- Jan Vandenbussche, Erik Lauwers, K. Uyttenhove, Michiel Steyaert, Georges G. E. Gielen:
Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter.
357-361
Electronic Edition (link) BibTeX
- Ricardo Carmona-Galán, Francisco Jiménez-Garrido, Rafael Domínguez-Castro, Servando Espejo-Meana, Ángel Rodríguez-Vázquez:
Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip.
362-367
Electronic Edition (link) BibTeX
BIST Diagnosis and DFT
Code and Memory Optimization in Co-Design
- Heiko Michel, Alexander Worm, Norbert Wehn, Michael Münch:
Hardware/Software Trade-Offs for Advanced 3G Channel Coding.
396-401
Electronic Edition (link) BibTeX
- Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil D. Dutt, Alexandru Nicolau:
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs.
402-408
Electronic Edition (link) BibTeX
- Stefan Steinke, Lars Wehmeyer, Bo-Sik Lee, Peter Marwedel:
Assigning Program and Data Objects to Scratchpad for Energy Reduction.
409-417
Electronic Edition (link) BibTeX
Network on a Chip
Low Power Architectures and Software
- Tanja Van Achteren, Geert Deconinck, Francky Catthoor, Rudy Lauwereins:
Data Reuse Exploration Techniques for Loop-Dominated Application.
428-535
Electronic Edition (link) BibTeX
- Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam:
EAC: A Compiler Framework for High-Level Energy Estimation and Optimization.
436-442
Electronic Edition (link) BibTeX
- Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau:
Power Savings in Embedded Processors through Decode Filer Cache.
443-448
Electronic Edition (link) BibTeX
- Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii:
Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors.
449-450
Electronic Edition (link) BibTeX
Nitty Gritty Details of Layout Design
SoC and System Test
- Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu:
Test Planning and Design Space Exploration in a Core-Based Environment.
478-485
Electronic Edition (link) BibTeX
- Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin:
A Hierarchical Test Scheme for System-On-Chip Designs.
486-490
Electronic Edition (link) BibTeX
- Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Efficient Wrapper/TAM Co-Optimization for Large SOCs.
491-498
Electronic Edition (link) BibTeX
- Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei:
Beyond UML to an End-of-Line Functional Test Engine.
499-505
Electronic Edition (link) BibTeX
Modelling and Synthesis of Embedded Systems
Panel - Power Crisis in SoC Design:
Strategies for Constructing Low-Power,
High-Performance SoC Designs
Reconfigurable Architectures
- Davide Rizzo, Osvaldo Colavin:
A Video Compression Case Study on a Reconfigurable VLIW Architecture.
540-546
Electronic Edition (link) BibTeX
- Marcos Sanchez-Elez, Milagros Fernández, Rafael Maestre, Rafael Maestre, Fadi J. Kurdahi, Román Hermida, Nader Bagherzadeh:
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures.
547-552
Electronic Edition (link) BibTeX
- Gilles Sassatelli, Lionel Torres, Pascal Benoit, Thierry Gil, Camille Diou, Gaston Cambon, Jérôme Galy:
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications.
553-558
Electronic Edition (link) BibTeX
- Jürgen Teich, Markus Köster:
(Self-)reconfigurable Finite State Machines: Theory and Implementation.
559-567
Electronic Edition (link) BibTeX
Analogue Modelling,
Layout and Sizing
Test Resource Partitioning for Embedded Cores
System Level Simulation and Modelling
Deep Submicron Design and Timing Closure
Reconfigurable SoC - What Will it Look Like?
Layout Aware Logic Synthesis
Buffering and Tapering
Automatic Design Debug and TPG
Object Oriented System Specification and Design
UML:
Using the Unified Modeling Language for Embedded System Specification
Real-Time Embedded Systems
Interconnect Modelling
- David Goren, Michael Zelikson, Tiberiu C. Galambos, Rachel Gordin, Betty Livshitz, Alon Amir, Anatoly Sherman, Israel A. Wagner:
An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach .
804-811
Electronic Edition (link) BibTeX
- Lauren Hui Chen, Malgorzata Marek-Sadowska:
Closed-Form Crosstalk Noise Metrics for Physical Design Applications.
812-819
Electronic Edition (link) BibTeX
- Qinwei Xu, Pinaki Mazumder:
Formulation of Low-Order Dominant Poles for Y-Matrix of Interconnects.
820-825
Electronic Edition (link) BibTeX
- Bernard N. Sheehan:
Library Compatible Ceff for Gate-Level Timing.
826-831
Electronic Edition (link) BibTeX
On-Line Testing and Fault Tolerance
- Cecilia Metra, Luca Schiano, Bruno Riccò, Michele Favalli:
Self-Checking Scheme for the On-Line Testing of Power Supply Noise.
832-836
Electronic Edition (link) BibTeX
- Régis Leveugle:
Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance.
837-841
Electronic Edition (link) BibTeX
- Kaijie Wu, Ramesh Karri:
Exploiting Idle Cycles for Algorithm Level Re-Computing.
842-846
Electronic Edition (link) BibTeX
- Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López:
New Techniques for Speeding-Up Fault-Injection Campaigns.
847-853
Electronic Edition (link) BibTeX
Design Space Evaluation
- Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst:
System Design for Flexibility.
854-861
Electronic Edition (link) BibTeX
- Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee:
Accurate Area and Delay Estimators for FPGAs.
862-869
Electronic Edition (link) BibTeX
- Klaus Buchenrieder, Andreas Pyttel, Alexander Sedlmeier:
A Powerful System Design Methodology Combining OCAPI and Handel-C for Concept Engineering.
870-874
Electronic Edition (link) BibTeX
- Nick Savoiu, Sandeep K. Shukla, Rajesh K. Gupta:
Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level Simulation.
875-883
Electronic Edition (link) BibTeX
From System Specification to Layout:
Seamless Top-Down Design Methods for Analogue and Mixed Signal Applications
Architectural Level Synthesis
Advanced Linear Modelling Techniques
Memory Testing and ATPG Issues
Embedded Software Performance Analysis and Optimization
Technical Plenary - 40 Years of EDA
Design Technology for Networked Reconfigurable FPGA Platforms
High-Level Synthesis and Asynchronous Pipelines
Coupling and Switching Noise Modelling within Integrated Circuits
Formal Verification Techniques:
Industrial Status and Perspectives
Power Optimization for Embedded Processor
Poster Sessions
- Walter Hartong, Lars Hedrich, Erich Barke:
An Approach to Model Checking for Nonlinear Analog Systems.
1080
Electronic Edition (link) BibTeX
- Slawomir Pilarski, Gracia Hu:
Speeding up SAT for EDA.
1081
Electronic Edition (link) BibTeX
- Fadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah:
Search-Based SAT Using Zero-Suppressed BDDs.
1082
Electronic Edition (link) BibTeX
- Manuel Martínez, Maria J. Avedillo, José M. Quintana, H. Süß, Manfred Koegst:
An Encoding Technique for Low Power CMOS Implementations of Controllers.
1083
Electronic Edition (link) BibTeX
- Elena Dubrova:
Composition Trees in Finding Best Variable Orderings for ROBDDs.
1084
Electronic Edition (link) BibTeX
- Joerg Abke, Erich Barke:
A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs .
1085
Electronic Edition (link) BibTeX
- Peyman Rezvani, Massoud Pedram:
Concurrent and Selective Logic Extraction with Timing Consideration.
1086
Electronic Edition (link) BibTeX
- Dariusz Kania:
Improved Technology Mapping for PAL-Based Devices Using a New Approach to Multi-Output Boolean Functions.
1087
Electronic Edition (link) BibTeX
- Michel R. C. M. Berkelaar, Koen van Eijk:
Efficient and Effective Redundancy Removal for Million-Gate Circuits.
1088
Electronic Edition (link) BibTeX
- Alexandre V. Bystrov, Maciej Koutny, Alexandre Yakovlev:
Visualization of Partial Order Models in VLSI Design Flow.
1089
Electronic Edition (link) BibTeX
- Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana:
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems.
1090
Electronic Edition (link) BibTeX
- Jie S. Hu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
Power-Efficient Trace Caches.
1091
Electronic Edition (link) BibTeX
- Mahmut T. Kandemir, Ibrahim Kolcu:
Reducing Cache Access Energy in Array-Intensive Application.
1092
Electronic Edition (link) BibTeX
- Carsten Nitsch, Udo Kebschull:
The Use of Runtime Configuration Capabilities for Networked Embedded Systems.
1093
Electronic Edition (link) BibTeX
- Iouliia Skliarova, António de Brito Ferrari:
A SAT Solver Using Software and Reconfigurable Hardware.
1094
Electronic Edition (link) BibTeX
- Ralf Münzenberger, Matthias Dörfel, Frank Slomka, Richard Hofmann:
A New Time Model for the Specification, Design, Validation and Synthesis of Embedded Real-Time Systems.
1095
Electronic Edition (link) BibTeX
- Martin Grajcar, Werner Grass:
Improved Constraints for Multiprocessor System Scheduling.
1096
Electronic Edition (link) BibTeX
- Olga Peñalba, José M. Mendías, Román Hermida:
Maximizing Conditonal Reuse by Pre-Synthesis Transformations.
1097
Electronic Edition (link) BibTeX
- Sunan Tugsinavisut, Peter A. Beerel:
Control Circuit Templates for Asynchronous Bundled-Data Pipelines.
1098
Electronic Edition (link) BibTeX
- Olivier Peyran, Wenjun Zhuang:
Transforming Arbitrary Structures into Topologically Equivalent Slicing Structures.
1099
Electronic Edition (link) BibTeX
- Chih-Hung Lee, Yu-Chung Lin, Wen-Yu Fu, Chung-Chiao Chang, Tsai-Ming Hsieh:
A New Formulation for SOC Floorplan Area Minimization Problem.
1100
Electronic Edition (link) BibTeX
- Chris C. N. Chu, Evangeline F. Y. Young:
Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design.
1101
Electronic Edition (link) BibTeX
- Yazdan Aghaghiri, Massoud Pedram, Farzan Fallah:
EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses.
1102
Electronic Edition (link) BibTeX
- Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner:
Estimation of Power Consumption in Encoded Data Buses.
1103
Electronic Edition (link) BibTeX
- Tran chi Hieu:
Optimization Techniques for Design of General and Feedback Linear Analog Amplifier with Symbolic Analysis.
1104
Electronic Edition (link) BibTeX
- Antonio Luchetta, Stefano Manetti, Maria Cristina Piccirilli:
Critical Comparison among Some Analog Fault Diagnosis Procedures Based on Symbolic Techniques.
1105
Electronic Edition (link) BibTeX
- Mircea R. Stan, Avishek Panigrahi:
The Selective Pull-Up (SP) Noise Immunity Scheme for Dynamic Circuits.
1106
Electronic Edition (link) BibTeX
- Andreia Cathelin, D. Saias, Didier Belot, Y. Leclercq, F. Clément:
Substrate Parasitic Extraction for RF Integrated Circuits.
1107
Electronic Edition (link) BibTeX
- David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin:
A Complete Phase-Locked Loop Power Consumption Model.
1108
Electronic Edition (link) BibTeX
- Cristinel Ababei, Kia Bazargan:
Statistical Timing Driven Partitioning for VLSI Circuits.
1109
Electronic Edition (link) BibTeX
- Kenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen:
DAISY-CT: A High-Level Simulation Tool for Continuous-Time Delta Sigma Modulators.
1110
Electronic Edition (link) BibTeX
- A. Hassibi, Maria del Mar Hershenson:
Automated Optimal Design of Switched-Capacitor Filters.
1111
Electronic Edition (link) BibTeX
- Tao Lin, Michael W. Beattie, Lawrence T. Pileggi:
On-Chip Inductance Models: 3D or Not 3D?
1112
Electronic Edition (link) BibTeX
- Hasan Ymeri, Bart Nauwelaers, Karen Maex, David De Roest, Michele Stucchi, Servaas Vandenberghe:
Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate.
1113
Electronic Edition (link) BibTeX
- Roni Khazaka, Michel S. Nakhla:
Compact Macromodel for Lossy Coupled Transmission Lines.
1114
Electronic Edition (link) BibTeX
- Jean-Luc Levant, Mohammed Ramdani:
An EMC-Compliant Design Method of High-Density Integrated Circuits.
1115
Electronic Edition (link) BibTeX
- Irith Pomeranz, Janusz Rajski, Sudhakar M. Reddy:
Finding a Common Fault Response for Diagnosis during Silicon Debug.
1116
Electronic Edition (link) BibTeX
- Suriya Ashok Kumar, Rafic Z. Makki, David Binkley:
IDDT Testing of Embedded CMOS SRAMs.
1117
Electronic Edition (link) BibTeX
- Swarup Bhunia, Kaushik Roy:
Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis.
1118
Electronic Edition (link) BibTeX
- Jun-Weir Lin, Chung-Len Lee, Jwu E. Chen:
An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits.
1119
Electronic Edition (link) BibTeX
- Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet:
On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems.
1120
Electronic Edition (link) BibTeX
- Rohit Kapur, Thomas W. Williams, M. Ray Mercer:
Directed-Binary Search in Logic BIST Diagnostics.
1121
Electronic Edition (link) BibTeX
- Michele Favalli, Marcello Dalpasso:
An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern Generators.
1122
Electronic Edition (link) BibTeX
- Irith Pomeranz, Yervant Zorian:
Fault Isolation Using Tests for Non-Isolated Blocks.
1123
Electronic Edition (link) BibTeX
- Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre:
A Heuristic for Test Scheduling at System Level.
1124
Electronic Edition (link) BibTeX
- Sandeep Koranne, Vishal Suhas Choudhary:
Formulation of SOC Test Scheduling as a Network Transportation Problem.
1125
Electronic Edition (link) BibTeX
- Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira:
A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-Based FPGAs.
1126
Electronic Edition (link) BibTeX
- Alexander V. Drozd, M. V. Lobachev, J. V. Drozd:
Efficient On-Line Testing Method for a Floating-Point Iterative Array Divider.
1127
Electronic Edition (link) BibTeX
- Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon:
An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores.
1128
Electronic Edition (link) BibTeX
- Anton Sauer, Günter Elst, Ludger Krahn, Werner John:
The Fraunhofer Knowledge Network (FKN) for Training in Critical Design Disciplines.
1129
Electronic Edition (link) BibTeX
- Leandro Soares Indrusiak, Manfred Glesner, Ricardo Augusto da Luz Reis:
Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments.
1130
Electronic Edition (link) BibTeX
- Bernd Stöhr, Michael Simmons, Joachim Geishauser:
FlexBench: Reuse of Verification IP to Increase Productivity.
1131
Electronic Edition (link) BibTeX
- Juha-Pekka Soininen, Jari Kreku, Yang Qu:
Mappability Estimation of Architecture and Algorithm.
1132
Electronic Edition (link) BibTeX
- Peter R. Wilson, J. Neil Ross, Mark Zwolinski, Andrew D. Brown, Yavuz Kiliç:
Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS.
1133
Electronic Edition (link) BibTeX
- Klaus Hering:
A Parallel LCC Simulation System.
1134
Electronic Edition (link) BibTeX
- Francesco Bruschi, Michele Chiamenti, Fabrizio Ferrandi, Donatella Sciuto:
Error Simulation Based on the SystemC Design Description Language.
1135
Electronic Edition (link) BibTeX
- Dag Björklund, Johan Lilius:
Towards a Kernel Language for Heterogeneous Computing.
1136
Electronic Edition (link) BibTeX
- Lukai Cai, Daniel Gajski, Paul Kritzinger, Mike Olivarez:
Top-Down System Level Design Methodology Using SpecC, VCC and SystemC.
1137
Electronic Edition (link) BibTeX
- Laura Pozzi, Miljan Vuletic, Paolo Ienne:
Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors.
1138
Electronic Edition (link) BibTeX
- Hans Georg Brachtendorf, S. Lampe, Rainer Laur, Robert C. Melville, Peter Feldmann:
Steady State Calculation of Oscillators Using Continuation Methods.
1139
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:05:45 2009
by Michael Ley (ley@uni-trier.de)