| 2008 |
|---|
| 60 | EE | Paolo Maistri,
Régis Leveugle:
Double-Data-Rate Computation as a Countermeasure against Fault Analysis.
IEEE Trans. Computers 57(11): 1528-1539 (2008) |
| 2007 |
|---|
| 59 | EE | Régis Leveugle,
Abdelaziz Ammari,
V. Maingot,
E. Teyssou,
Pascal Moitrel,
Christophe Mourtel,
Nathalie Feyt,
Jean-Baptiste Rigaud,
Assia Tria:
Experimental evaluation of protections against laser-induced faults and consequences on fault modeling.
DATE 2007: 1587-1592 |
| 58 | EE | Michele Portolan,
Régis Leveugle:
Effective Checkpoint and Rollback Using Hardware/OS Collaboration.
DFT 2007: 370-378 |
| 57 | EE | Paolo Maistri,
Pierre Vanhauwaert,
Régis Leveugle:
Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections.
DFT 2007: 499-507 |
| 56 | EE | Paolo Maistri,
Pierre Vanhauwaert,
Régis Leveugle:
A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection.
FDTC 2007: 54-61 |
| 55 | EE | Yannick Monnet,
Marc Renaudin,
Régis Leveugle:
Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs.
IOLTS 2007: 113-120 |
| 54 | EE | Régis Leveugle:
Early Analysis of Fault-based Attack Effects in Secure Circuits.
IEEE Trans. Computers 56(10): 1431-1434 (2007) |
| 2006 |
|---|
| 53 | | Régis Leveugle,
V. Maingot:
On the Use of Information Redundancy When Designing Secure Chips.
DDECS 2006: 141-142 |
| 52 | | Pierre Vanhauwaert,
Régis Leveugle,
Philippe Roche:
A Flexible SoPC-based Fault Injection Environment.
DDECS 2006: 192-197 |
| 51 | EE | Abdelaziz Ammari,
Régis Leveugle,
B. Nicolescu,
Yvon Savaria:
Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection.
DELTA 2006: 488-493 |
| 50 | EE | Yannick Monnet,
Marc Renaudin,
Régis Leveugle,
Christophe Clavier,
Pascal Moitrel:
Case Study of a Fault Attack on Asynchronous DES Crypto-Processors.
FDTC 2006: 88-97 |
| 49 | EE | Yannick Monnet,
Marc Renaudin,
Régis Leveugle,
Nathalie Feyt,
Pascal Moitrel,
F. M'Buwa Nzenguet:
Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor.
IOLTS 2006: 125-130 |
| 48 | EE | Pierre Vanhauwaert,
Régis Leveugle,
Philippe Roche:
Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis.
VLSI-SoC 2006: 391-396 |
| 47 | EE | Yannick Monnet,
Marc Renaudin,
Régis Leveugle:
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic.
IEEE Trans. Computers 55(9): 1104-1115 (2006) |
| 2005 |
|---|
| 46 | EE | Yannick Monnet,
Marc Renaudin,
Régis Leveugle:
Asynchronous circuits transient faults sensitivity evaluation.
DAC 2005: 863-868 |
| 45 | EE | Michele Portolan,
Régis Leveugle:
Towards a Secure and Reliable System.
EUC 2005: 1085-1098 |
| 44 | EE | Régis Leveugle:
Introduction to the Special Session on Secure Implementations.
IOLTS 2005: 115 |
| 43 | EE | Yannick Monnet,
Marc Renaudin,
Régis Leveugle:
Hardening Techniques against Transient Faults for Asynchronous Circuits.
IOLTS 2005: 129-134 |
| 42 | EE | Régis Leveugle,
Yervant Zorian,
Luca Breveglieri,
André K. Nieuwland,
Klaus Rothbart,
Jean-Pierre Seifert:
On-Line Testing for Secure Implementations: Design and Validation.
IOLTS 2005: 211 |
| 41 | EE | Michele Portolan,
Régis Leveugle:
On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors.
IOLTS 2005: 247-252 |
| 40 | EE | Régis Leveugle:
A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations.
IOLTS 2005: 260-265 |
| 39 | EE | Lorena Anghel,
Régis Leveugle,
Pierre Vanhauwaert:
Evaluation of SET and SEU Effects at Multiple Abstraction Levels.
IOLTS 2005: 309-312 |
| 38 | EE | Abdelaziz Ammari,
K. Hadjiat,
Régis Leveugle:
Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation.
J. Electronic Testing 21(4): 365-376 (2005) |
| 2004 |
|---|
| 37 | EE | Régis Leveugle,
Abdelaziz Ammari:
Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow.
DATE 2004: 590-595 |
| 36 | EE | Régis Leveugle,
D. Cimonnet,
Abdelaziz Ammari:
System-Level Dependability Analysis with RT-Level Fault Injection Accuracy.
DFT 2004: 451-458 |
| 35 | EE | Yannick Monnet,
Marc Renaudin,
Régis Leveugle:
Asynchronous Circuits Sensitivity to Fault Injection.
IOLTS 2004: 121-128 |
| 34 | EE | Michele Portolan,
Régis Leveugle:
Operating System Function Reuse to Achieve Low-Cost Fault Tolerance.
IOLTS 2004: 167-174 |
| 33 | EE | Abdelaziz Ammari,
K. Hadjiat,
Régis Leveugle:
On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation.
IOLTS 2004: 227-232 |
| 2003 |
|---|
| 32 | EE | Abdelaziz Ammari,
Régis Leveugle,
Matteo Sonza Reorda,
Massimo Violante:
Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels.
DFT 2003: 336-343 |
| 31 | EE | Régis Leveugle,
Lörinc Antoni,
Béla Fehér:
Dependability Analysis: A New Application for Run-Time Reconfiguration.
IPDPS 2003: 173 |
| 30 | EE | Régis Leveugle,
K. Hadjiat:
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments.
J. Electronic Testing 19(5): 559-575 (2003) |
| 29 | EE | Régis Leveugle,
Glenn H. Chapman:
Special section on defect and fault tolerance in VLSI systems.
Microelectronics Journal 34(1): 1 (2003) |
| 2002 |
|---|
| 28 | EE | Régis Leveugle:
Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance.
DATE 2002: 837-841 |
| 27 | EE | Lörinc Antoni,
Régis Leveugle,
Béla Fehér:
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes.
DFT 2002: 245-253 |
| 26 | EE | Régis Leveugle,
K. Hadjiat:
Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study.
IOLTW 2002: 107-111 |
| 2001 |
|---|
| 25 | EE | Régis Leveugle:
A Low-Cost Hardware Approach to Dependability Validation of Ips.
DFT 2001: 242-249 |
| 24 | EE | Raoul Velazco,
Régis Leveugle,
O. Calvo:
Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results.
DFT 2001: 259- |
| 23 | EE | Régis Leveugle,
R. Cercueil:
High Level Modifications of VHDL Descriptions for On-Line Test or Fault Tolerance.
DFT 2001: 84- |
| 2000 |
|---|
| 22 | EE | Lörinc Antoni,
Régis Leveugle,
Béla Fehér:
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes.
DFT 2000: 405-413 |
| 21 | EE | Régis Leveugle:
Fault Injection in VHDL Descriptions and Emulation.
DFT 2000: 414- |
| 1999 |
|---|
| 20 | EE | Alejandro Chagoya,
Régis Leveugle:
Experiments on Multimedia Support of VLSI Design teaching in the MODEM Project.
MSE 1999: 82-83 |
| 1997 |
|---|
| 19 | EE | X. Wendling,
H. Chauvet,
Lionel Revéret,
R. Rochet,
Régis Leveugle:
Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance Capabilities.
DFT 1997: 195-203 |
| 1996 |
|---|
| 18 | EE | X. Wendling,
R. Rochet,
Régis Leveugle:
Standard and ROM-based synthesis of FSMs with control flow checking capabilities.
VTS 1996: 81-86 |
| 1994 |
|---|
| 17 | | Régis Leveugle,
R. Rochet,
Gabriele Saucier:
Alternative Approaches to Fault Detection in FSMs.
DFT 1994: 271-279 |
| 16 | | T. Michel,
Régis Leveugle,
Gabriele Saucier,
R. Doucet,
P. Chapier:
Taking Advantage of ASICs to Improve Dependability with Very Low Overheads.
EDAC-ETC-EUROASIC 1994: 14-18 |
| 15 | | C. Safinia,
Régis Leveugle,
Gabriele Saucier:
Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling.
EDAC-ETC-EUROASIC 1994: 349-353 |
| 14 | | Régis Leveugle,
Zahava Koren,
Israel Koren,
Gabriele Saucier,
Norbert Wehn:
The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis.
IEEE Trans. Computers 43(12): 1398-1406 (1994) |
| 1993 |
|---|
| 13 | EE | Régis Leveugle:
Optimized State Assignment of single fault Tolerant FSMs Based on SEC Codes.
DAC 1993: 14-18 |
| 12 | | R. Rochet,
Régis Leveugle,
Gabriele Saucier:
Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes.
DFT 1993: 9-16 |
| 11 | | Régis Leveugle,
R. Rochet,
Gabriele Saucier,
L. Martinez,
C. Pitot:
A Synthesis Tool for Fault-Tolerant Finite State Machines.
FTCS 1993: 502-511 |
| 10 | | Régis Leveugle,
X. Delord,
Gabriele Saucier:
Influence of Error Correlations on the Signature Analysis Aliasing.
ICCD 1993: 584-587 |
| 9 | | Régis Leveugle:
Test of single fault tolerant controllers in VLSI circuits.
VLSI 1993: 123-132 |
| 1992 |
|---|
| 8 | | Régis Leveugle,
C. Safina:
Generation of optimized datapaths: bit-slice versus standard cells.
Synthesis for Control Dominated Circuits 1992: 153-166 |
| 7 | | C. Safina,
Régis Leveugle:
Clocking scheme selection for circuits made up of a controller and a datapath.
Synthesis for Control Dominated Circuits 1992: 293-308 |
| 6 | | Pierre Abouzeid,
Régis Leveugle,
Gabriele Saucier:
Logic Synthesis for Automatic Layout.
Synthesis for Control Dominated Circuits 1992: 335-343 |
| 5 | | L. Gerbaux,
Régis Leveugle,
Gabriele Saucier:
Synthesis of large controllers using ROM or PLA generators.
Synthesis for Control Dominated Circuits 1992: 47-59 |
| 1991 |
|---|
| 4 | | T. Michel,
Régis Leveugle,
Gabriele Saucier:
A New Approach to Control Flow Checking Without Program Modification.
FTCS 1991: 334-343 |
| 3 | | Margot Karam,
Régis Leveugle,
Gabriele Saucier:
Hierarchical Test Generation Based on Delayed Propagation.
ITC 1991: 739-747 |
| 1990 |
|---|
| 2 | | Régis Leveugle,
Gabriele Saucier:
Optimized Synthesis of Concurrently Checked Controllers.
IEEE Trans. Computers 39(4): 419-425 (1990) |
| 1989 |
|---|
| 1 | | Régis Leveugle,
Gabriele Saucier:
Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities.
ITC 1989: 355-363 |
