| 2008 |
|---|
| 209 | EE | Andre Guntoro,
Manfred Glesner:
Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filters.
ASAP 2008: 299-304 |
| 208 | EE | Faizal Arya Samman,
Thomas Hollstein,
Manfred Glesner:
Multicast Parallel Pipeline Router Architecture for Network-on-Chip.
DATE 2008: 1396-1401 |
| 207 | EE | Massoud Momeni,
Petru Bogdan Bacinschi,
Manfred Glesner:
Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation.
DATE 2008: 688-693 |
| 206 | EE | Petru Bogdan Bacinschi,
Tudor Murgan,
Klaus Koch,
Manfred Glesner:
An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs.
DATE 2008: 698-703 |
| 205 | EE | Enkhbold Ochirsuren,
Heiko Hinkelmann,
Leandro Soares Indrusiak,
Manfred Glesner:
TinyOS Extensions for a Wireless Sensor Network Node Based on a Dynamically Reconfigurable Processor.
DIPES 2008: 161-170 |
| 204 | EE | Sven Eisenhardt,
Thomas Schweizer,
Julio A. de Oliveira Filho,
Tobias Oppold,
Wolfgang Rosenstiel,
Alexander Thomas,
Jürgen Becker,
Frank Hannig,
Dmitrij Kissler,
Hritam Dutta,
Jürgen Teich,
Heiko Hinkelmann,
Peter Zipf,
Manfred Glesner:
Coarse-grained reconfiguration.
FPL 2008: 349 |
| 203 | EE | Heiko Hinkelmann,
Peter Zipf,
Manfred Glesner,
Matthias Alles,
Timo Vogt,
Norbert Wehn,
Götz Kappen,
Tobias G. Noll:
Application-specific reconfigurable processors.
FPL 2008: 350 |
| 202 | EE | Andre Guntoro,
Manfred Glesner:
A lifting-based DWT and IDWT processor with multi-context configuration and normalization factor.
FPL 2008: 479-482 |
| 201 | EE | Andre Guntoro,
Manfred Glesner:
High-performance fpga-based floating-point adder with three inputs.
FPL 2008: 627-630 |
| 200 | EE | Enkhbold Ochirsuren,
Leandro Soares Indrusiak,
Manfred Glesner:
An Actor-Oriented Group Mobility Model for Wireless Ad Hoc Sensor Networks.
ICDCS Workshops 2008: 174-179 |
| 199 | EE | Faizal Arya Samman,
Thomas Hollstein,
Manfred Glesner:
Flexible parallel pipeline network-on-chip based on dynamic packet identity management.
IPDPS 2008: 1-8 |
| 198 | EE | Sujan Pandey,
Rolf Drechsler,
Tudor Murgan,
Manfred Glesner:
Process variations aware robust on-chip bus architecture synthesis for MPSoCs.
ISCAS 2008: 2989-2992 |
| 197 | EE | Leandro Soares Indrusiak,
Luciano Ost,
Leandro Möller,
Fernando Moraes,
Manfred Glesner:
Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects.
ISVLSI 2008: 491-494 |
| 196 | EE | Alberto García Ortiz,
Leandro Soares Indrusiak,
Tudor Murgan,
Manfred Glesner:
PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels.
PATMOS 2008: 219-228 |
| 195 | EE | Luciano Ost,
Fernando Gehm Moraes,
Leandro Möller,
Leandro Soares Indrusiak,
Manfred Glesner,
Sanna Määttä,
Jari Nurmi:
A simplified executable model to evaluate latency and throughput of networks-on-chip.
SBCCI 2008: 170-175 |
| 194 | EE | Manfred Glesner,
Tudor Murgan,
Thomas Hollstein:
Hardware Based Rapid Prototyping.
Wiley Encyclopedia of Computer Science and Engineering 2008 |
| 193 | EE | Radu Dogaru,
Manfred Glesner:
A fast and compact classifier based on sorting in an iteratively expanded input space.
Int. J. Intell. Syst. 23(5): 607-618 (2008) |
| 2007 |
|---|
| 192 | | Gilles Sassatelli,
Manfred Glesner,
Christophe Bobda,
Pascal Benoit:
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2007, Montpellier, France, June 2007
Univ. Montpellier II 2007 |
| 191 | EE | Leandro Soares Indrusiak,
Andreas Thuy,
Manfred Glesner:
Interactive presentation: Executable system-level specification models containing UML-based behavioral patterns.
DATE 2007: 301-306 |
| 190 | EE | Peter Zipf,
Heiko Hinkelmann,
Lei Deng,
Manfred Glesner,
Holger Blume,
Tobias G. Noll:
A Power Estimation Model for an FPGA-based Softcore Processor.
FPL 2007: 171-176 |
| 189 | EE | Mihail Petrov,
Manfred Glesner:
A Scalable Resampling Architecture.
GLOBECOM 2007: 3102-3106 |
| 188 | EE | Mihail Petrov,
Manfred Glesner:
An Efficient Fractional-Rate Interpolation Architecture.
GLOBECOM 2007: 4554-4558 |
| 187 | EE | José Carlos S. Palma,
Leandro Soares Indrusiak,
Fernando Gehm Moraes,
Alberto García Ortiz,
Manfred Glesner,
Ricardo A. L. Reis:
Inserting Data Encoding Techniques into NoC-Based Systems.
ISVLSI 2007: 299-304 |
| 186 | EE | Tudor Murgan,
Petru Bogdan Bacinschi,
Sujan Pandey,
Alberto García Ortiz,
Manfred Glesner:
On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects.
PATMOS 2007: 242-254 |
| 185 | | Heiko Hinkelmann,
Tudor Murgan,
G. Liu,
Peter Zipf,
Manfred Glesner:
On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication.
ReCoSoC 2007: 185-191 |
| 184 | | Kurt Franz Ackermann,
Leandro Soares Indrusiak,
Manfred Glesner:
System Level Design of a Dynamically Self-Reconfigurable Image Processing System.
ReCoSoC 2007: 47-54 |
| 183 | | Peter Zipf,
Heiko Hinkelmann,
Felix Missel,
Manfred Glesner:
A Customizable LEON2-Based VLIW Processor.
ReCoSoC 2007: 55-60 |
| 182 | | Tudor Murgan,
Andre Guntoro,
Heiko Hinkelmann,
Petru Bogdan Bacinschi,
Manfred Glesner:
Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling.
ReCoSoC 2007: 7-14 |
| 181 | EE | Leandro Soares Indrusiak,
Manfred Glesner:
Specification of alternative execution semantics of UML sequence diagrams within actor-oriented models.
SBCCI 2007: 330-335 |
| 180 | EE | Thomas Hollstein,
Manfred Glesner:
Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms.
Computers & Electrical Engineering 33(4): 310-319 (2007) |
| 179 | EE | Sujan Pandey,
Manfred Glesner:
Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic.
IEEE Trans. VLSI Syst. 15(10): 1111-1124 (2007) |
| 178 | EE | Heiko Hinkelmann,
Peter Zipf,
Manfred Glesner,
Thilo Pionteck:
Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme).
it - Information Technology 49(3): 174- (2007) |
| 2006 |
|---|
| 177 | | Gilles Sassatelli,
Leandro Soares Indrusiak,
Manfred Glesner,
Lionel Torres:
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2006, Montpellier, France, July 2006
Univ. Montpellier II 2006 |
| 176 | EE | Heiko Hinkelmann,
Peter Zipf,
Manfred Glesner:
Design Concepts for a Dynamically ReconfigurableWireless Sensor Node.
AHS 2006: 436-441 |
| 175 | EE | Andre Guntoro,
Peter Zipf,
Oliver Soffke,
Harald Klingbeil,
Martin Kumm,
Manfred Glesner:
Implementation of Realtime and Highspeed Phase Detector on FPGA.
ARC 2006: 1-11 |
| 174 | | Heiko Hinkelmann,
Peter Zipf,
Manfred Glesner:
A metric for the energy-efficiency of dynamically reconfigurable systems.
ARCS Workshops 2006: 152-161 |
| 173 | EE | Sujan Pandey,
Manfred Glesner:
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint.
DAC 2006: 663-668 |
| 172 | EE | Oliver Soffke,
Peter Zipf,
Tudor Murgan,
Manfred Glesner:
A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits.
DATE 2006: 632-637 |
| 171 | EE | Peter Zipf,
Manfred Glesner:
Towards an Automated Design of Application-specific Reconfigurable Logic.
Dynamically Reconfigurable Architectures 2006 |
| 170 | EE | Andreas Thuy,
Leandro Soares Indrusiak,
Manfred Glesner:
Applying Communication Patterns to Actor-Oriented Models.
FDL 2006: 407-409 |
| 169 | EE | Sujan Pandey,
Manfred Glesner:
Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture.
FPL 2006: 1-6 |
| 168 | EE | Heiko Hinkelmann,
Andreas Gunberg,
Peter Zipf,
Leandro Soares Indrusiak,
Manfred Glesner:
Multitasking Support for Dynamically Reconfig Urable Systems.
FPL 2006: 1-6 |
| 167 | EE | Tudor Murgan,
Massoud Momeni,
Alberto García Ortiz,
Manfred Glesner:
A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects.
ICCAD 2006: 323-328 |
| 166 | EE | Murthy Palla,
Klaus Koch,
Jens Bargfrede,
Manfred Glesner,
Walter Anheier:
Reduction of Crosstalk Pessimism using Tendency Graph Approach.
ICCD 2006 |
| 165 | EE | Sujan Pandey,
Manfred Glesner:
Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique.
ISCAS 2006 |
| 164 | EE | José Carlos S. Palma,
Ricardo A. L. Reis,
Leandro Soares Indrusiak,
Alberto García Ortiz,
Manfred Glesner,
Fernando Gehm Moraes:
Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip.
ISVLSI 2006: 426-427 |
| 163 | EE | Romualdo Begale Prudencio,
Leandro Soares Indrusiak,
Manfred Glesner:
An Efficient Hardware Implementation of a Self-Adaptable Equalizer for WCDMA Downlink UMTS Standard.
ISVLSI 2006: 77-84 |
| 162 | EE | Tudor Murgan,
Petru Bogdan Bacinschi,
Alberto García Ortiz,
Manfred Glesner:
Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance.
PATMOS 2006: 169-180 |
| 161 | EE | Clemens Schlachta,
Manfred Glesner:
A CMOS Compatible Charge Recovery Logic Family for Low Supply Voltages.
PATMOS 2006: 563-572 |
| 160 | EE | José Carlos S. Palma,
Leandro Soares Indrusiak,
Fernando Gehm Moraes,
Alberto García Ortiz,
Manfred Glesner,
Ricardo A. L. Reis:
Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry.
PATMOS 2006: 603-613 |
| 159 | | Heiko Hinkelmann,
Peter Zipf,
Manfred Glesner:
A Concept for a Profile-based Dynamic Reconfiguration Mechanism.
ReCoSoC 2006: 105-110 |
| 158 | | Hua Zhong,
Leandro Soares Indrusiak,
Heiko Hinkelmann,
Manfred Glesner:
Exploring Functional Unit Parallelism in Reconfigurable Computing Platforms.
ReCoSoC 2006: 160-167 |
| 157 | | Kurt Franz Ackermann,
Friedhelm Mayer,
Leandro Soares Indrusiak,
Manfred Glesner:
Adaptable Image Processing System based on FPGA Modular Multi Kernel Instantiations.
ReCoSoC 2006: 183-188 |
| 156 | EE | Sujan Pandey,
Nurten Utlu,
Manfred Glesner:
Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture.
VLSI-SoC 2006: 222-227 |
| 155 | EE | Sujan Pandey,
Tudor Murgan,
Manfred Glesner:
Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis.
VLSI-SoC 2006: 296-301 |
| 154 | EE | Tudor Murgan,
O. Mitrea,
Sujan Pandey,
Petru Bogdan Bacinschi,
Manfred Glesner:
Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters.
VLSI-SoC 2006: 302-307 |
| 2005 |
|---|
| 153 | | Gilles Sassatelli,
Manfred Glesner,
Lionel Torres,
Leandro Soares Indrusiak,
Thomas Hollstein:
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2005, Montpellier, France, June 2005
Univ. Montpellier II 2005 |
| 152 | | Heiko Hinkelmann,
Thilo Pionteck,
Oliver Kleine,
Manfred Glesner:
Prozessorintegration und Speicheranbindung dynamisch rekonfigurierbarer Funktionseinheiten.
ARCS Workshops 2005: 45-51 |
| 151 | EE | Sorin Cotofana,
Alexandre Schmid,
Yusuf Leblebici,
Adrian M. Ionescu,
Oliver Soffke,
Peter Zipf,
Manfred Glesner,
A. Rubio:
CONAN - A Design Exploration Framework for Reliable Nano-Electronics.
ASAP 2005: 260-267 |
| 150 | | Peter Zipf,
Oliver Soffke,
Andre Schumacher,
Radu Dogaru,
Manfred Glesner:
Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata.
FPL 2005: 329-334 |
| 149 | | Peter Zipf,
Oliver Soffke,
Andre Schumacher,
Clemens Schlachta,
Radu Dogaru,
Manfred Glesner:
A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata.
FPL 2005: 335-340 |
| 148 | | Sujan Pandey,
Manfred Glesner,
Max Mühlhäuser:
On-Chip Communication Topology Synthesis for a Shared Memory Architecture.
FPL 2005: 374-379 |
| 147 | | Mihail Petrov,
Manfred Glesner:
Optimal FFT Architecture Selection for OFDM Receivers on FPGA.
FPT 2005: 313-314 |
| 146 | | Mihail Petrov,
Manfred Glesner:
A State-Serial Viterbi Decoder Architecture for Digital Radio on FPGA.
FPT 2005: 323-324 |
| 145 | | Peter Zipf,
Oliver Soffke,
Michael Velten,
Manfred Glesner:
Abstrakte Modellierung der Eigenschaften von nanoelektronischen CNT-Elementen in SystemC.
GI Jahrestagung (1) 2005: 329-333 |
| 144 | | Clemens Schlachta,
Oliver Soffke,
Peter Zipf,
Manfred Glesner:
Eine weiterentwickelte quasi-statische adiabatische Logikfamilie.
GI Jahrestagung (1) 2005: 448 |
| 143 | | Martin K. F. Schafer,
Thomas Hollstein,
Heiko Zimmer,
Manfred Glesner:
Deadlock-free routing and component placement for irregular mesh-based networks-on-chip.
ICCAD 2005: 238-245 |
| 142 | EE | Leandro Soares Indrusiak,
Romualdo Begale Prudencio,
Manfred Glesner:
Modeling and Prototyping of Communication Systems Using Java: A Case Study.
IEEE International Workshop on Rapid System Prototyping 2005: 225-231 |
| 141 | EE | Heiko Zimmer,
Stefan Zink,
Thomas Hollstein,
Manfred Glesner:
Buffer-Architecture Exploration for Routers in a Hierarchical Network-on-Chip.
IPDPS 2005 |
| 140 | EE | Sujan Pandey,
Heiko Zimmer,
Manfred Glesner,
Max Mühlhäuser:
High level hardware/software communication estimation in shared memory architecture.
ISCAS (1) 2005: 37-40 |
| 139 | EE | Alberto García Ortiz,
Tudor Murgan,
Mihail Petrov,
Manfred Glesner:
A linear model for high-level delay estimation in VDSM on-chip interconnects.
ISCAS (2) 2005: 1078-1081 |
| 138 | EE | A. Petrov,
Tudor Murgan,
Peter Zipf,
Manfred Glesner:
Functional modeling techniques for a wireless LAN OFDM transceiver.
ISCAS (4) 2005: 3970-3973 |
| 137 | EE | Diego Fernando Jimenez Orostegui,
Leandro Soares Indrusiak,
Manfred Glesner:
Proxy-Based Integration of Reconfigurable Hardware Within Simulation Environments: Improving E-Learning Experience in Microelectronics.
MSE 2005: 59-60 |
| 136 | | Tudor Murgan,
Abdulfattah Mohammad Obeid,
Andre Guntoro,
Peter Zipf,
Manfred Glesner,
Ulrich Heinkel:
Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks.
ReCoSoC 2005: 151-156 |
| 135 | | Peter Zipf,
Claude Stötzler,
Manfred Glesner:
Analysis and Architectural Study of a Hybrid ASIC/Configurable State Machine Model.
ReCoSoC 2005: 53-58 |
| 134 | | Leandro Soares Indrusiak,
Manfred Glesner:
Experiences on Actor-oriented Design of Reconfigurable Systems.
ReCoSoC 2005: 79-84 |
| 133 | | Thomas Hollstein,
Sujan Pandey,
Manfred Glesner:
Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip.
ReCoSoC 2005: 85-92 |
| 132 | EE | Manfred Glesner,
Heiko Hinkelmann,
Thomas Hollstein,
Leandro Soares Indrusiak,
Tudor Murgan,
Abdulfattah Mohammad Obeid,
Mihail Petrov,
Thilo Pionteck,
Peter Zipf:
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques.
SAMOS 2005: 12-21 |
| 131 | EE | Sujan Pandey,
Manfred Glesner,
Max Mühlhäuser:
Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture.
SBCCI 2005: 230-235 |
| 130 | EE | Elvio Dutra,
Leandro Soares Indrusiak,
Manfred Glesner:
Non-linear addressing scheme for a lookup-based transformation function in a reconfigurable noise generator.
SBCCI 2005: 242-247 |
| 129 | EE | Thilo Pionteck,
Thomas Stiefmeier,
Thorsten Staake,
Manfred Glesner:
On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction.
VLSI-SoC 2005: 283-297 |
| 128 | EE | Cristian Chitu,
Manfred Glesner:
An FPGA implementation of the AES-Rijndael in OCB/ECB modes of operation.
Microelectronics Journal 36(2): 139-146 (2005) |
| 2004 |
|---|
| 127 | | Thilo Pionteck,
Thomas Stiefmeier,
Thorsten Staake,
Lukusa D. Kabulepa,
Manfred Glesner:
Integration dynamisch rekonfigurierbarer Funktionseinheiten in Prozessoren.
ARCS Workshops 2004: 155-164 |
| 126 | EE | Manfred Glesner,
Thomas Hollstein,
Leandro Soares Indrusiak,
Peter Zipf,
Thilo Pionteck,
Mihail Petrov,
Heiko Zimmer,
Tudor Murgan:
Reconfigurable platforms for ubiquitous computing.
Conf. Computing Frontiers 2004: 377-389 |
| 125 | EE | Tudor Murgan,
Mihail Petrov,
Mateusz Majer,
Peter Zipf,
Manfred Glesner,
Ulrich Heinkel,
Jörg Pleickhardt,
Bernd Bleisteiner:
Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing.
Conf. Computing Frontiers 2004: 404-418 |
| 124 | EE | Thilo Pionteck,
Thorsten Staake,
Thomas Stiefmeier,
Lukusa D. Kabulepa,
Manfred Glesner:
On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs.
FPGA 2004: 258 |
| 123 | EE | Thilo Pionteck,
Thomas Stiefmeier,
Thorsten Staake,
Manfred Glesner:
A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals.
FPL 2004: 1090-1092 |
| 122 | EE | Ralf Ludewig,
Oliver Soffke,
Peter Zipf,
Manfred Glesner,
Kong Pang Pun,
Kuen Hung Tsoi,
Kin-Hong Lee,
Philip Heng Wai Leong:
IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter.
FPL 2004: 526-535 |
| 121 | EE | Mihail Petrov,
Tudor Murgan,
F. May,
Martin Vorbach,
Peter Zipf,
Manfred Glesner:
The XPP Architecture and Its Co-simulation Within the Simulink Environment.
FPL 2004: 761-770 |
| 120 | EE | Ralf Ludewig,
Thomas Hollstein,
Falko Schütz,
Manfred Glesner:
Rapid Prototyping of an Integrated Testing and Debugging Unit.
IEEE International Workshop on Rapid System Prototyping 2004: 187-192 |
| 119 | | Thilo Pionteck,
Thorsten Staake,
Thomas Stiefmeier,
Lukusa D. Kabulepa,
Manfred Glesner:
Design of a reconfigurable AES encryption/decryption engine for mobile terminals.
ISCAS (2) 2004: 545-548 |
| 118 | | Mihail Petrov,
Tudor Murgan,
Abdulfattah Mohammad Obeid,
Cristian Chitu,
Peter Zipf,
Jörg Brakensiek,
Manfred Glesner:
Dynamic power optimization of the trace-back process for the Viterbi algorithm.
ISCAS (2) 2004: 721-724 |
| 117 | EE | Peter Zipf,
Claude Stötzler,
Manfred Glesner:
A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture.
ISVLSI 2004: 266-267 |
| 116 | EE | Tudor Murgan,
Alberto García Ortiz,
Clemens Schlachta,
Heiko Zimmer,
Mihail Petrov,
Manfred Glesner:
On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects.
PATMOS 2004: 819-828 |
| 115 | EE | Alberto García Ortiz,
Tudor Murgan,
Manfred Glesner:
Moment-Based Estimation of Switching Activity for Correlated Distributions.
PATMOS 2004: 859-868 |
| 114 | EE | Tudor Murgan,
Clemens Schlachta,
Mihail Petrov,
Leandro Soares Indrusiak,
Alberto García Ortiz,
Manfred Glesner,
Ricardo A. L. Reis:
Accurate capture of timing parameters in inductively-coupled on-chip interconnects.
SBCCI 2004: 117-122 |
| 113 | EE | Peter Zipf,
Heiko Hinkelmann,
Adeel Ashraf,
Manfred Glesner:
A switch architecture and signal synchronization for GALS system-on-chips.
SBCCI 2004: 210-215 |
| 112 | | Leandro Soares Indrusiak,
Manfred Glesner,
Ricardo Augusto da Luz Reis:
Lookup-based Remote Laboratory for FPGA Digital Design Prototyping.
VIRTUAL-LAB 2004: 3-11 |
| 111 | EE | O. Mitrea,
Manfred Glesner:
A power-constrained design strategy for CMOS tuned low noise amplifiers.
Microelectronics Reliability 44(5): 877-883 (2004) |
| 110 | | Leandro Soares Indrusiak,
Ricardo A. L. Reis,
Manfred Glesner:
Um Framework de Apoio à Colaboração no Projeto Distribuído de Sistemas Integrados.
RITA 11(2): 49-74 (2004) |
| 2003 |
|---|
| 109 | | Manfred Glesner,
Ricardo Augusto da Luz Reis,
Hans Eveking,
Vincent John Mooney III,
Leandro Soares Indrusiak,
Peter Zipf:
IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003
Technische Universität Darmstadt, Insitute of Microelectronic Systems 2003 |
| 108 | EE | Leandro Soares Indrusiak,
Florian Lubitz,
Ricardo Augusto da Luz Reis,
Manfred Glesner:
Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues.
DATE 2003: 10940-10945 |
| 107 | EE | Leandro Soares Indrusiak,
R. Reis,
Manfred Glesner:
Supporting Consistency Control between Functional and Structural Views in Interface-based Design Models.
FDL 2003: 364-373 |
| 106 | EE | Stephan Bingemer,
Peter Zipf,
Manfred Glesner:
A granularity-based classification model for systems-on-a-chip.
FPGA 2003: 239 |
| 105 | EE | Tudor Murgan,
Mihail Petrov,
Alberto García Ortiz,
Ralf Ludewig,
Peter Zipf,
Thomas Hollstein,
Manfred Glesner,
Bernard Ölkrug,
Jörg Brakensiek:
Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures.
FPL 2003: 1111-1114 |
| 104 | EE | Alberto García Ortiz,
Lukusa D. Kabulepa,
Tudor Murgan,
Manfred Glesner:
Moment-Based Power Estimation in Very Deep Submicron Technologies.
ICCAD 2003: 107-112 |
| 103 | EE | Thilo Pionteck,
A. Garcya,
Lukusa D. Kabulepa,
Manfred Glesner:
The requirement for flexibility in IP-based designs increasesHardware Evaluation of Low Power Communication Mechanisms for Transport-Triggered Architectures.
IEEE International Workshop on Rapid System Prototyping 2003: 141-147 |
| 102 | EE | Ralf Ludewig,
Alberto García Ortiz,
Tudor Murgan,
Juan Jesus,
Ocampo Hidalgo,
Manfred Glesner:
Emulation of Analog Components for the Rapid Prototyping of Wireless Baseband Systems.
IEEE International Workshop on Rapid System Prototyping 2003: 172-178 |
| 101 | EE | Radu Dogaru,
Ioana Dogaru,
Manfred Glesner:
Compact image compression using simplicial and ART neural systems with mixed signal implementations.
ISCAS (5) 2003: 689-692 |
| 100 | EE | Leandro Soares Indrusiak,
Manfred Glesner,
Ricardo Augusto da Luz Reis,
Giuliana Alcántara,
Stefan Hoermann,
Ralf Steinmetz:
Reducing Authoring Costs of Online Training in Microelectronics Design by Reusing Design Documentation Content.
MSE 2003: 57-58 |
| 99 | EE | Alberto García Ortiz,
Lukusa D. Kabulepa,
Manfred Glesner:
Switching Activity Estimation in Non-linear Architectures.
PATMOS 2003: 269-278 |
| 98 | EE | Alberto García Ortiz,
Tudor Murgan,
Manfred Glesner:
Transition Activity Estimation for General Correlated Data Distributions.
VLSI Design 2003: 440-445 |
| 97 | | Thilo Pionteck,
Lukusa D. Kabulepa,
Manfred Glesner:
Exploring the Capabilities of Reconfigurable Hardware for OFDM-based WLANs.
VLSI-SOC 2003: 161-166 |
| 96 | | Mihail Petrov,
Abdulfattah Mohammad Obeid,
Tudor Murgan,
Peter Zipf,
Jörg Brakensiek,
Bernard Ölkrug,
Manfred Glesner:
An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders.
VLSI-SOC 2003: 167- |
| 95 | | Radu Dogaru,
Cristian Chitu,
Manfred Glesner:
A Versatile Cellular Neural Circuit Based on a Multi-nested Approach: Functional Capabilities and Applications.
VLSI-SOC 2003: 356-361 |
| 94 | | Thomas Hollstein,
Ralf Ludewig,
Christoph Mager,
Peter Zipf,
Manfred Glesner:
A hierarchical generic approach for on-chip communication, testing and debugging of SoCs.
VLSI-SOC 2003: 44-49 |
| 93 | | Stephan Bingemer,
Peter Zipf,
Manfred Glesner:
An Integrated Model Bridging the Gap between Technology and Economy.
VLSI-SOC 2003: 442- |
| 92 | | Cristian Chitu,
Manfred Glesner:
High Performance of an AES-Rijndael ASIC working in OCB/ECB Modes of Operation.
VLSI-SOC 2003: 62-67 |
| 2002 |
|---|
| 91 | | Manfred Glesner,
Peter Zipf,
Michel Renovell:
Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings
Springer 2002 |
| 90 | EE | Jochen Mades,
Manfred Glesner:
Regularization of hierarchical VHDL-AMS models using bipartite graphs.
DAC 2002: 548-551 |
| 89 | EE | Alberto García Ortiz,
Lukusa D. Kabulepa,
Manfred Glesner:
Estimation of Power Consumption in Encoded Data Buses.
DATE 2002: 1103 |
| 88 | EE | Leandro Soares Indrusiak,
Manfred Glesner,
Ricardo Augusto da Luz Reis:
Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments.
DATE 2002: 1130 |
| 87 | EE | Chun Hok Ho,
Philip Heng Wai Leong,
Kuen Hung Tsoi,
Ralf Ludewig,
Peter Zipf,
Alberto García Ortiz,
Manfred Glesner:
Fly - A Modifiable Hardware Compiler.
FPL 2002: 381-390 |
| 86 | EE | Thilo Pionteck,
Peter Zipf,
Lukusa D. Kabulepa,
Manfred Glesner:
A Framework for Teaching (Re)Configurable Architectures in Student Projects.
FPL 2002: 444-451 |
| 85 | EE | Peter Zipf,
Manfred Glesner,
Christine Bauer,
Hans Wojtkowiak:
Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension.
FPL 2002: 586-595 |
| 84 | EE | Ralf Ludewig,
Alberto García Ortiz,
Tudor Murgan,
Manfred Glesner:
Power Estimation Based on Transition Activity Analysis with an Architecture Precise Rapid Prototyping System.
IEEE International Workshop on Rapid System Prototyping 2002: 138- |
| 83 | EE | Chun Hok Ho,
M. P. Leong,
Philip Heng Wai Leong,
Jürgen Becker,
Manfred Glesner:
Rapid Prototyping of FPGA Based Floating Point DSP Systems.
IEEE International Workshop on Rapid System Prototyping 2002: 19-24 |
| 82 | EE | Abdulfattah Mohammad Obeid,
Alberto García Ortiz,
Ralf Ludewig,
Manfred Glesner:
Prototyping of a High Performance Generic Viterbi Decoder.
IEEE International Workshop on Rapid System Prototyping 2002: 42-47 |
| 81 | EE | Thilo Pionteck,
N. Toender,
Lukusa D. Kabulepa,
Manfred Glesner,
T. Kella:
On the Rapid Prototyping of Equalizers for OFDM Systems.
IEEE International Workshop on Rapid System Prototyping 2002: 48-52 |
| 80 | EE | Lukusa D. Kabulepa,
Alberto García Ortiz,
Manfred Glesner:
Power reduction techniques for an OFDM burst synchronization core.
ISCAS (1) 2002: 265-268 |
| 79 | EE | Lukusa D. Kabulepa,
Alberto García Ortiz,
Manfred Glesner:
Design of an efficient OFDM burst synchronization scheme.
ISCAS (3) 2002: 449-452 |
| 78 | EE | Jochen Mades,
D. E. Schwarz,
Manfred Glesner:
A discrete algorithm for the regularization of hierarchical VHDL-AMS models.
ISCAS (5) 2002: 477-480 |
| 77 | EE | Alberto García Ortiz,
Lukusa D. Kabulepa,
Manfred Glesner:
Efficient estimation of signal transition activity in MAC architectures.
ISLPED 2002: 319-322 |
| 2001 |
|---|
| 76 | EE | Jürgen Becker,
Nicolas Liebau,
Thilo Pionteck,
Manfred Glesner:
Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures.
FPL 2001: 584-589 |
| 75 | EE | Amar Mukherjee,
Nitin Motgi,
Jürgen Becker,
A. Friebe,
C. Habermann,
Manfred Glesner:
Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems.
IEEE International Workshop on Rapid System Prototyping 2001: 58-63 |
| 74 | EE | B. Voss,
Manfred Glesner:
A low power sinusoidal clock.
ISCAS (4) 2001: 108-111 |
| 73 | EE | Jochen Mades,
T. Schneider,
A. Windisch,
Thomas Hollstein,
Jürgen Becker,
Manfred Glesner:
Concept of a Joint University/Industry Course for Mixed-Signal System-On-Chip Design.
MSE 2001: 2-3 |
| 72 | | Leandro Soares Indrusiak,
Jürgen Becker,
Manfred Glesner,
Ricardo Augusto da Luz Reis:
Distributed Collaborative Design over Cave2 Framework.
VLSI-SOC 2001: 97-108 |
| 71 | | Jürgen Becker,
Manfred Glesner:
A Parallel Dynamically Reconfigurable Architecture Designed for Flexible Application-Tailored Hardware/Software Systems in Future Mobile Communication.
The Journal of Supercomputing 19(1): 105-127 (2001) |
| 2000 |
|---|
| 70 | EE | Ahmad Alsolaim,
Janusz A. Starzyk,
Jürgen Becker,
Manfred Glesner:
Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems.
FCCM 2000: 205-216 |
| 69 | EE | Jürgen Becker,
Thilo Pionteck,
Manfred Glesner:
DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications.
FPL 2000: 312-321 |
| 68 | EE | Frank-Michael Renner,
Jürgen Becker,
Manfred Glesner:
Field Programmable Communication Emulation and Optimization for Embedded System Design.
FPL 2000: 58-67 |
| 67 | | Matthias Rychetsky,
John Shawe-Taylor,
Manfred Glesner:
Direct Bayes Point Machines.
ICML 2000: 815-822 |
| 66 | EE | Frank-Michael Renner,
Jürgen Becker,
Manfred Glesner:
Automated Communication Synthesis for Architecture-Precise Rapid Prototyping of Real-Time Embedded Systems.
IEEE International Workshop on Rapid System Prototyping 2000: 154-159 |
| 65 | EE | Jürgen Becker,
Lukusa D. Kabulepa,
Frank-Michael Renner,
Manfred Glesner:
Simulation and Rapid Prototyping of Flexible Systems-on-a-Chip for Future Mobile Communication Applications.
IEEE International Workshop on Rapid System Prototyping 2000: 160- |
| 64 | EE | Ulrich Mayer,
Manfred Glesner:
Hardware Accelerated Estimation of Multiplexer-Introduced Loss for MPEG-4 Data Streams.
IEEE International Workshop on Rapid System Prototyping 2000: 214- |
| 63 | EE | Ulrich Mayer,
Jürgen Deicke,
Manfred Glesner:
Estimation of Multiplexer-Introduced Loss for MPEG-4 Data Streams Connected to (R)CBR Channels.
ISCC 2000: 298-303 |
| 62 | | Jürgen Becker,
Manfred Glesner,
Ahmad Alsolaim,
Janusz A. Starzyk:
Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures.
PDPTA 2000 |
| 61 | | Jürgen Becker,
Manfred Glesner:
IP-based Application Mapping Techniques for Dynamically Reconfigurable Hardware Architectures.
PDPTA 2000 |
| 60 | | Thuyen Le,
Manfred Glesner:
Flexible architectures for DCT of variable-length targeting shape-adaptive transform.
IEEE Trans. Circuits Syst. Video Techn. 10(8): 1489-1495 (2000) |
| 1999 |
|---|
| 59 | | Marc Theisen,
Jürgen Becker,
Manfred Glesner,
Tri Caohuu:
Parallel Hardware Compilation in Complex Hardware/Software Systems based on High-Level Code Transformations.
ARCS 1999: 143-154 |
| 58 | EE | Peter Gerken,
Stefan Schultz,
Gerald Knabe,
Franco Casalino,
Gianluca Di Cagno,
Mauro Quaglia,
Jean-Claude Dufourd,
Souhila Boughoufalah,
Frédéric Bouilhaguet,
Michael Stepping,
Thomas Bonse,
Ulrich Mayer,
Jürgen Deicke,
Manfred Glesner:
MPEG-4 PC - Authoring and Playing of MPEG-4 Content for Local and Broadcast Applications.
ECMAST 1999: 108-119 |
| 57 | | Tri Caohuu,
Thuy Trong Le,
Manfred Glesner,
Jürgen Becker:
Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching.
FPL 1999: 507-513 |
| 56 | EE | Frank-Michael Renner,
Jürgen Becker,
Manfred Glesner:
Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems.
IEEE International Workshop on Rapid System Prototyping 1999: 108-113 |
| 55 | | Andreas Kirschbaum,
Jürgen Becker,
Manfred Glesner:
ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect.
VLSI 1999: 659-670 |
| 54 | | Bernard Courtois,
Jean-Michel Karam,
Salvador Mir,
Marcelo Lubaszewski,
Vladimir Székely,
Márta Rencz,
Klaus Hofmann,
Manfred Glesner:
Design and Test of MEMs.
VLSI Design 1999: 270- |
| 53 | EE | Michael Gasteier,
Manfred Glesner:
Bus-based communication synthesis on system level.
ACM Trans. Design Autom. Electr. Syst. 4(1): 1-11 (1999) |
| 52 | EE | Alexander Steudel,
Manfred Glesner:
Fuzzy segmented image coding using orthonormal bases and derivative chain coding.
Pattern Recognition 32(11): 1827-1841 (1999) |
| 1998 |
|---|
| 51 | EE | Thomas Hollstein,
Jürgen Becker,
Andreas Kirschbaum,
Manfred Glesner:
HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems.
CODES 1998: 29-33 |
| 50 | EE | Michael Gasteier,
Manfred Glesner,
Michael Münch:
Generation of Interconnect Topologies for Communication Synthesis.
DATE 1998: 36- |
| 49 | EE | Manfred Glesner,
Matthias Rychetsky,
Stefan Ortmann:
Advanced Hardware and Software Architectures for Computational Intelligence: Application to a Real World Problem.
EUROMICRO 1998: 21068- |
| 48 | EE | Frank-Michael Renner,
Jürgen Becker,
Manfred Glesner:
An FPFA Implementation of a Magnetic Bearing Controller for Mechatronic Applications.
FPL 1998: 179-188 |
| 47 | EE | Jürgen Becker,
Andreas Kirschbaum,
Frank-Michael Renner,
Manfred Glesner:
Perspectives of Reconfigurable Computing in Research, Industry and Education.
FPL 1998: 39-48 |
| 46 | EE | Jürgen Deicke,
Ulrich Mayer,
A. Knoll,
Manfred Glesner:
Flexible Multiplexing in MPEG-4 Systems.
IDMS 1998: 83-94 |
| 45 | | Andreas Kirschbaum,
Jürgen Becker,
Manfred Glesner:
A Reconfigurable Hardware-Monitor for Communication Analysis in Distributed Real-Time Systems.
IPPS/SPDP Workshops 1998: 61-66 |
| 44 | EE | Andreas Kirschbaum,
Stefan Ortmann,
Manfred Glesner:
Rapid Prototyping of a Co-Processor Based Engine Knock Detection System.
International Workshop on Rapid System Prototyping 1998: 124-129 |
| 43 | EE | Andreas Kirschbaum,
Jürgen Becker,
Manfred Glesner:
Run-Time Monitoring of Communication Activities in a Rapid Prototyping Environment.
International Workshop on Rapid System Prototyping 1998: 52-57 |
| 42 | | Matthias Rychetsky,
Stefan Ortmann,
Manfred Glesner:
Pruning and Regularization Techniques for Feed Forward Nets Applied on a Real World Data Base.
NC 1998: 603-609 |
| 41 | | Stefan Ortmann,
Matthias Rychetsky,
Manfred Glesner:
Constructive Learning of a Sub-Feature Detector Network by Means of Prediction Risk Estimation.
NC 1998: 995-1001 |
| 40 | EE | Jürgen Deicke,
Ulrich Mayer,
Manfred Glesner:
A client/server application as an example for MPEG-4 systems.
Computer Communications 21(15): 1302-1309 (1998) |
| 39 | EE | Stefan Ortmann,
Manfred Glesner:
Development and Implementation of a Neural Knock Detector Using Constructive Learning Methods.
International Journal of Uncertainty, Fuzziness and Knowledge-Based Systems 6(2): 127-138 (1998) |
| 38 | | Hans-Jürgen Herpel,
Manfred Glesner:
Rapid Prototyping of Real-Time Information Processing Units for Mechatronic Systems.
Real-Time Systems 14(3): 269-291 (1998) |
| 1997 |
|---|
| 37 | | Wayne Luk,
Peter Y. K. Cheung,
Manfred Glesner:
Field-Programmable Logic and Applications, 7th International Workshop, FPL '97, London, UK, September 1-3, 1997, Proceedings
Springer 1997 |
| 36 | EE | Jean-Michel Karam,
Bernard Courtois,
Hicham Boutamine,
P. Drake,
András Poppe,
Vladimir Székely,
Márta Rencz,
Klaus Hofmann,
Manfred Glesner:
CAD and Foundries for Microsystems.
DAC 1997: 674-679 |
| 35 | EE | Klaus Hofmann,
Manfred Glesner,
Nicu Sebe,
A. Manolescu,
Santiago Marco,
Josep Samitier,
Jean-Michel Karam,
Bernard Courtois:
Generation of the HDL-A-model of a micromembrane from its finite-element-description.
ED&TC 1997: 108-112 |
| 34 | EE | M. Lang,
D. David,
Manfred Glesner:
Automatic transfer of parametric FEM models into CAD-layout formats for top-down design of microsystems.
ED&TC 1997: 200-204 |
| 33 | | Thomas Hollstein,
Andreas Kirschbaum,
Manfred Glesner:
A prototyping environment for fuzzy controllers.
FPL 1997: 482-490 |
| 32 | | Jürgen Deicke,
Ulrich Mayer,
Manfred Glesner:
An Object-Oriented Client/Server Architecture for Video-on-Demand Applications.
IDMS 1997: 440-449 |
| 31 | EE | Michael Münch,
Norbert Wehn,
Manfred Glesner:
An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions.
ACM Trans. Design Autom. Electr. Syst. 2(4): 344-364 (1997) |
| 1996 |
|---|
| 30 | | Reiner W. Hartenstein,
Manfred Glesner:
Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, 6th International Workshop on Field-Programmable Logic, FPL '96, Darmstadt, Germany, September 23-25, 1996, Proceedings
Springer 1996 |
| 29 | | Ulrike Ober,
Hans-Jürgen Herpel,
Manfred Glesner:
CAPpartx: Computer Aided Prototyping Partitioning for Xilinx FPGAs, a Hierarchical Partitioning Tool for Rapid Prototyping.
FPL 1996: 106-115 |
| 28 | EE | Michael Münch,
Manfred Glesner,
Norbert Wehn:
An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions.
ISSS 1996: 45-50 |
| 27 | EE | Michael Gasteier,
Manfred Glesner:
Bus-Based Communication Synthesis on System-Level.
ISSS 1996: 65-70 |
| 1995 |
|---|
| 26 | EE | Ulrike Ober,
Manfred Glesner:
Multiway netlist partitioning onto FPGA-based board architecture.
EURO-DAC 1995: 150-155 |
| 25 | | U. Zahm,
Thomas Hollstein,
Hans-Jürgen Herpel,
Norbert Wehn,
Manfred Glesner:
Advanced Method for Industry Related Education with an FPGA Design Self-Learning Kit.
FPL 1995: 241-250 |
| 24 | | Hans-Jürgen Herpel,
Ulrike Ober,
Manfred Glesner:
Prototype Generation of Application-Specific Embedded Controllers for Microsystems.
FPL 1995: 341-351 |
| 23 | EE | Saman K. Halgamuge,
Christoph Grimm,
Manfred Glesner:
A sub Bayesian nearest prototype neural network with fuzzy interpretability for diagnosis problems.
SAC 1995: 445-449 |
| 22 | EE | Thomas A. Runkler,
Manfred Glesner:
Multidimensional defuzzification - fast algorithms for the determination of crisp characteristic subsets.
SAC 1995: 575-579 |
| 21 | EE | Saman K. Halgamuge,
Alain Brichard,
Manfred Glesner:
Comparison of a heuristic method with a genetic algorithm for generation of compact rule based classifiers.
SAC 1995: 580-585 |
| 20 | EE | Saman K. Halgamuge,
Werner Poechmueller,
Manfred Glesner:
An alternative approach for generation of membership functions and fuzzy rules based on radial and cubic basis function networks.
Int. J. Approx. Reasoning 12(3-4): 279-298 (1995) |
| 19 | EE | Saman K. Halgamuge,
Manfred Glesner:
Fuzzy neural networks: between functional equivalence and applicability.
Int. J. Neural Syst. 6(2): 185-196 (1995) |
| 1994 |
|---|
| 18 | EE | Michael Held,
Manfred Glesner:
Generating compilers for generated datapaths.
EURO-DAC 1994: 532-537 |
| 17 | EE | Wolfgang Ecker,
Manfred Glesner,
Andreas Vombach:
Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations.
EURO-DAC 1994: 624-629 |
| 16 | | Thomas Hollstein,
Saman K. Halgamuge,
Andreas Kirschbaum,
Manfred Glesner:
Rapid-Prototyping von anwendungsspezifischen Fuzzy Controllern mit Field Programmable Gate Arrays.
Fuzzy Days 1994: 8-14 |
| 15 | | Hans-Jürgen Herpel,
Michael Held,
Manfred Glesner:
A Design Methodology for the Conceptual Design of Application Specific Digital Processors in Mechatronic Systems.
HICSS (1) 1994: 78-86 |
| 14 | | Hans-Jürgen Herpel,
Michael Held,
Manfred Glesner:
MCEMS Toolbox - A Hardware-in-the-Loop Simulation Environment for Mechatronic Systems.
MASCOTS 1994: 356-357 |
| 13 | EE | Saman K. Halgamuge,
Manfred Glesner:
Fuzzy neural fusion techniques for industrial applications.
SAC 1994: 136-141 |
| 12 | EE | Thomas A. Runkler,
Manfred Glesner:
DECADE - fast centroid approximation defuzzification for real time fuzzy control applications.
SAC 1994: 161-165 |
| 11 | EE | H. Genther,
Manfred Glesner:
Automatic generation of a fuzzy classification system using fuzzy clustering methods.
SAC 1994: 180-183 |
| 1993 |
|---|
| 10 | | Norbert Wehn,
Manfred Glesner,
C. Vielhauer:
Estimating lower hardware bounds in high-level synthesis.
VLSI 1993: 261-270 |
| 1992 |
|---|
| 9 | | Peter Poechmueller,
Hans-Jürgen Herpel,
Manfred Glesner,
Fang Longsen:
High Level Synthesis in an FPL-Based Computer Aided Prototyping Environment.
FPL 1992: 96-105 |
| 1991 |
|---|
| 8 | | Peter Poechmueller,
Manfred Glesner:
A New Approach for Designing Fault-Tolerant Array Processors.
Fault-Tolerant Computing Systems 1991: 324-331 |
| 7 | | A. Laudenbach,
Manfred Glesner,
Norbert Wehn:
A VLSI System Design for the Control of High Performance Combustion Engines.
VLSI 1991: 247-256 |
| 1990 |
|---|
| 6 | | Norbert Wehn,
Manfred Glesner,
A. Kister,
S. Kastner:
Timing Driven Partitioning of Combinational Logic.
Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme 1990: 42-51 |
| 5 | | Werner Poechmueller,
Manfred Glesner:
Evaluation of state-of-the-art neural network customized hardware.
Neurocomputing 2(5): 209-231 (1990) |
| 1988 |
|---|
| 4 | EE | Norbert Wehn,
Manfred Glesner,
K. Caesar,
P. Mann,
A. Roth:
A Defect-Tolerant and Fully Testable PLA.
DAC 1988: 22-33 |
| 3 | | Manfred Glesner,
M. Huch,
Peter A. Ivey,
T. Midwinter,
Gabriele Saucier,
Jacques Trilhe:
Entwurf eines systolischen Arrays in Wafer Scale Technik für die digitale Signalverarbeitung.
GI Jahrestagung (2) 1988: 75-91 |
| 1987 |
|---|
| 2 | EE | Johannes Schuck,
Norbert Wehn,
Manfred Glesner,
G. Kamp:
The ALGIC Silicon Compiler System: Implementation, Design Experience and Results.
DAC 1987: 370-375 |
| 1986 |
|---|
| 1 | EE | Manfred Glesner,
Johannes Schuck,
R. B. Steck:
SCAT - a new statistical timing verifier in a silicon compiler system.
DAC 1986: 220-226 |
